公开(公告)号：US20120040517A1

公开(公告)日：2012-02-16

申请号：US13278010

申请日：2011-10-20

申请人： Witold MASZARA ,  Hemant ADHIKARI

发明人： Witold MASZARA ,  Hemant ADHIKARI

IPC分类号： H01L21/20 ,  H01L21/302

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

摘要翻译： 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

公开(公告)号：US20110081764A1

公开(公告)日：2011-04-07

申请号：US12575344

申请日：2009-10-07

申请人： Witold MASZARA ,  Hemant ADHIKARI

发明人： Witold MASZARA ,  Hemant ADHIKARI

IPC分类号： H01L21/762 ,  H01L21/20

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

摘要翻译： 提供了制造半导体器件的方法。 一种方法包括形成覆盖在本体衬底上的第一半导体材料层，并形成覆盖第一半导体材料层的第二半导体材料层。 该方法还包括在第二半导体材料的层上形成鳍状图案掩模，并使用鳍状图案掩模作为蚀刻掩模，各向异性蚀刻第二半导体材料的层和第一半导体材料的层。 各向异性蚀刻导致由第二半导体材料形成的翅片和鳍下方的第一半导体材料的暴露区域。 该方法还包括在鳍片下方的第一半导体材料的暴露区域中形成隔离层。

公开(公告)号：US20110062443A1

公开(公告)日：2011-03-17

申请号：US12560938

申请日：2009-09-16

申请人： Witold MASZARA

发明人： Witold MASZARA

IPC分类号： H01L29/786 ,  H01L21/321 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/458 ,  H01L29/66772 ,  H01L29/78654

摘要： Embodiments of a method for fabricating a semiconductor device are provided. In one embodiment, the method includes the step of producing a partially-completed semiconductor device including a substrate, source/drain (S/D) regions, a channel region between the S/D regions, a gate stack over the channel region, and sidewall spacers laterally adjacent the gate stack. The method further includes the steps of amorphizing the S/D regions, depositing a silicide-forming material over the amorphized S/D regions, and heating the partially-completed semiconductor device to a predetermined temperature at which the silicide-forming material reacts with the amorphized S/D regions.

摘要翻译： 提供了制造半导体器件的方法的实施例。 在一个实施例中，该方法包括产生部分完成的半导体器件的步骤，该半导体器件包括衬底，源极/漏极（S / D）区域，S / D区域之间的沟道区域，沟道区域上的栅极堆叠，以及 横向隔离件横向邻近门堆叠。 该方法还包括以下步骤：使S / D区域非晶化，在非晶化S / D区域上沉积硅化物形成材料，并将部分完成的半导体器件加热至预定温度，在该温度下硅化物形成材料与 非晶化S / D区域。

公开(公告)号：US07871873B2

公开(公告)日：2011-01-18

申请号：US12413174

申请日：2009-03-27

申请人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

发明人： Witold Maszara ,  Ming-Ren Lin ,  Jin Cho ,  Zoran Krivokapic

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/66795

摘要： A method of manufacturing semiconductor fins for a semiconductor device may begin by providing a bulk semiconductor substrate. The method continues by growing a layer of first epitaxial semiconductor material on the bulk semiconductor substrate, and by growing a layer of second epitaxial semiconductor material on the layer of first epitaxial semiconductor material. The method then creates a fin pattern mask on the layer of second epitaxial semiconductor material. The fin pattern mask has features corresponding to a plurality of fins. Next, the method anisotropically etches the layer of second epitaxial semiconductor material, using the fin pattern mask as an etch mask, and using the layer of first epitaxial semiconductor material as an etch stop layer. This etching step results in a plurality of fins formed from the layer of second epitaxial semiconductor material.

摘要翻译： 制造用于半导体器件的半导体鳍片的方法可以通过提供体半导体衬底开始。 该方法通过在体半导体衬底上生长第一外延半导体材料层并通过在第一外延半导体材料层上生长第二外延半导体材料层来继续。 该方法然后在第二外延半导体材料层上产生鳍状图案掩模。 翅片图形掩模具有对应于多个翅片的特征。 接下来，使用鳍图案掩模作为蚀刻掩模，并且使用第一外延半导体材料层作为蚀刻停止层，该方法各向异性地蚀刻第二外延半导体材料的层。 该蚀刻步骤导致由第二外延半导体材料层形成的多个鳍片。

公开(公告)号：US20060099752A1

公开(公告)日：2006-05-11

申请号：US10986399

申请日：2004-11-10

申请人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

发明人： Qi Xiang ,  Niraj Subba ,  Witold Maszara ,  Zoran Krivokapic ,  Ming-Ren Lin

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/78639 ,  H01L29/78684 ,  Y10S438/938

摘要： A semiconductor substrate is provided having an insulator thereon with a semiconductor layer on the insulator. A deep trench isolation is formed, introducing strain to the semiconductor layer. A gate dielectric and a gate are formed on the semiconductor layer. A spacer is formed around the gate, and the semiconductor layer and the insulator are removed outside the spacer. Recessed source/drain are formed outside the spacer.

摘要翻译： 提供了一种在绝缘体上具有半导体层的绝缘体的半导体衬底。 形成深沟槽隔离，向半导体层引入应变。 栅极电介质和栅极形成在半导体层上。 在栅极周围形成间隔物，并且将半导体层和绝缘体去除在间隔物的外部。 凹陷的源极/漏极形成在间隔物外部。

公开(公告)号：US06873030B2

公开(公告)日：2005-03-29

申请号：US10431008

申请日：2003-05-07

申请人： Witold Maszara ,  Zoran Krivokapic

发明人： Witold Maszara ,  Zoran Krivokapic

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L27/082 ,  H01L29/76

CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

摘要翻译： 通过提供衬底来制造半导体器件，并在衬底上提供介电层。 在电介质层上形成多晶硅体，在多晶硅体上设置金属层。 进行硅化处理以基本上硅化整个多晶硅体以在电介质上形成栅极。 在替代方法中，在多晶硅体上设置覆盖层，在硅化过程之前去除盖层。 在硅化过程之前，多晶硅体掺杂有选择的特性，在硅化过程期间，该掺杂剂被驱动到电介质层，以形成其邻近电介质的高浓度的栅极部分，该物质的类型和浓度 有助于确定形成的门的工作功能。

公开(公告)号：US06599831B1

公开(公告)日：2003-07-29

申请号：US10135227

申请日：2002-04-30

申请人： Witold Maszara ,  Zoran Krivokapic

发明人： Witold Maszara ,  Zoran Krivokapic

IPC分类号： H01L214763

CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659

摘要： A semiconductor device is fabricated by providing a substrate, and providing a dielectric layer on the substrate. A polysilicon body is formed on the dielectric layer, and a metal layer is provided on the polysilicon body. A silicidation process is undertaken to silicidize substantially the entire polysilicon body to form a gate on the dielectric. In an alternative process, a cap layer is provided on the polysilicon body, which cap layer is removed prior to the silicidation process. The polysilicon body is doped with a chosen specie prior to the silicidation process, which dopant, during the silicidation process, is driven toward the dielectric layer to form a gate portion having a high concentration thereof adjacent the dielectric, the type and concentration of this specie being instrumental in determining the work function of the formed gate.

摘要翻译： 通过提供衬底来制造半导体器件，并在衬底上提供介电层。 在电介质层上形成多晶硅体，在多晶硅体上设置金属层。 进行硅化处理以基本上硅化整个多晶硅体以在电介质上形成栅极。 在替代方法中，在多晶硅体上设置覆盖层，在硅化过程之前去除盖层。 在硅化过程之前，多晶硅体掺杂有选择的特性，在硅化过程期间，该掺杂剂被驱动到电介质层，以形成其邻近电介质的高浓度的栅极部分，该物质的类型和浓度 有助于确定形成的门的工作功能。

公开(公告)号：US06492209B1

公开(公告)日：2002-12-10

申请号：US09607629

申请日：2000-06-30

申请人： Srinath Krishnan ,  Matthew Buynoski ,  Witold Maszara

发明人： Srinath Krishnan ,  Matthew Buynoski ,  Witold Maszara

IPC分类号： H01L21302

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method for providing partially depleted and fully depleted transistor devices on the same semiconductor wafer. At least one trench is etched into a bulk semiconductor wafer. The wafer is then filled with an insulating material and polished down to the surface level of the semiconductor wafer to form a generally planar surface. A handle wafer is provided having a substrate layer and an insulating layer. The planar surface of the semiconductor wafer is bonded to the insulating layer of the handle wafer. The trench filled regions of the semiconductor wafer form regions of a first thickness and the remaining regions of the semiconductor wafer form regions of a second thickness. Fully depleted transistor device can then be formed in the regions of the first thickness and partially depleted transistor devices can be formed in regions of the second thickness.

摘要翻译： 一种用于在同一半导体晶片上提供部分耗尽和完全耗尽的晶体管器件的方法。 至少一个沟槽被蚀刻到体半导体晶片中。 然后将晶片填充绝缘材料并抛光至半导体晶片的表面水平以形成大致平坦的表面。 提供具有基底层和绝缘层的处理晶片。 半导体晶片的平面被接合到处理晶片的绝缘层上。 半导体晶片的沟槽填充区域形成第一厚度的区域，并且半导体晶片的其余区域形成第二厚度的区域。 然后可以在第一厚度的区域中形成完全耗尽的晶体管器件，并且可以在第二厚度的区域中形成部分耗尽的晶体管器件。

公开(公告)号：US06284608B1

公开(公告)日：2001-09-04

申请号：US09496245

申请日：2000-02-01

申请人： Zoran Krivakapic ,  Srinath Krishnan ,  Witold Maszara

发明人： Zoran Krivakapic ,  Srinath Krishnan ,  Witold Maszara

IPC分类号： H01L21336

CPC分类号： H01L29/66772 ,  H01L29/78696

摘要： A method of manufacturing an accumulation mode n-channel Silicon On Insulator (SOI) transistor includes forming an intrinsic silicon body region implanted with two deep Boron and one shallow Phosphorous implants; forming source/drain regions each implanted with Arsenic; and forming p-type regions adjacent each of the source and drain regions and disposed along the transistor channel. The SOI transistor has a higher transconductance than known SOI devices.

摘要翻译： 一种制造堆积模式n沟道绝缘体（SOI）晶体管的方法包括：形成植入两个深硼和一个浅磷植入物的本征硅体区域; 形成每个植入砷的源/漏区; 以及在所述源极和漏极区域中的每一个附近形成并且沿着所述晶体管沟道布置的p型区域。 SOI晶体管具有比已知SOI器件更高的跨导。

公开(公告)号：US5965917A

公开(公告)日：1999-10-12

申请号：US225248

申请日：1999-01-04

申请人： Witold Maszara ,  Srinath Krisnan

发明人： Witold Maszara ,  Srinath Krisnan

IPC分类号： H01L21/336 ,  H01L29/417 ,  H01L29/786 ,  H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/66772 ,  H01L29/41733 ,  H01L29/78615

摘要： A silicon-on-insulator MOSFET includes a silicon layer and an insulator layer positioned over a silicon substrate. An isolation region defines a silicon region positioned over the insulator layer. The silicon region further includes a source region, a drain region, and a doped body region. The drain region and source region do not extend to the bottom of the silicon region. A first metal conductor is electrically coupled to the side and top of the source region and the side of the body region. The first metal conductor establishes a potential at the body region to control floating body effects. A second metal conductor is electrically coupled to the top of the drain region.

摘要翻译： 绝缘体上硅MOSFET包括硅层和位于硅衬底上的绝缘体层。 隔离区域限定位于绝缘体层上方的硅区域。 硅区还包括源极区，漏极区和掺杂体区。 漏极区域和源极区域不延伸到硅区域的底部。 第一金属导体电耦合到源区域和身体区域的侧面的侧面和顶部。 第一金属导体在身体区域建立一个潜力来控制浮体效应。 第二金属导体电耦合到漏区的顶部。