公开(公告)号：US20070103009A1

公开(公告)日：2007-05-10

申请号：US11554515

申请日：2006-10-30

申请人： Xiao (Charles) Yang

发明人： Xiao (Charles) Yang

IPC分类号： H02K5/00 ,  H02K7/02 ,  H02K21/22

CPC分类号： H02K7/025 ,  H02N1/004 ,  H02N13/00 ,  Y02E60/16

摘要： The present invention relates to a method and device for fabricating an integrated flywheel device using semiconductor materials and IC/MEMS processes. Single crystal silicon has high energy storage/weight ratio and no defects. Single crystal silicon flywheel can operate at much higher speed than conventional flywheel. The integrated silicon flywheel is operated by electrostatic motor and supported by electrostatic bearings, which consume much less power than magnetic actuation in conventional flywheel energy storage systems. The silicon flywheel device is fabricated by IC and MEMS processes to achieve high device integration and low manufacturing cost. For the integrated silicon flywheel, high vacuum can be achieved using hermetic bonding methods such as eutectic, fusion, glass frit, SOG, anodic, covalent, etc. To achieve larger energy capacity, an array of silicon flywheels is fabricated on one substrate. Multiple layers of flywheel energy storage devices are stacked.

摘要翻译： 本发明涉及使用半导体材料和IC / MEMS工艺制造集成飞轮装置的方法和装置。 单晶硅具有高能量存储/重量比，无缺陷。 单晶硅飞轮可以以比传统飞轮高得多的速度运行。 集成的硅飞轮由静电电动机驱动并由静电轴承支撑，在传统的飞轮储能系统中消耗的功率远低于磁力驱动。 硅飞轮器件由IC和MEMS工艺制造，以实现高器件集成度和低制造成本。 对于集成硅飞轮，可以使用诸如共晶，熔合，玻璃料，SOG，阳极，共价等的密封接合方法实现高真空。为了实现更大的能量容量，在一个基板上制造了硅飞轮阵列。 堆叠多层飞轮储能装置。

公开(公告)号：US07160791B2

公开(公告)日：2007-01-09

申请号：US10931149

申请日：2004-08-30

申请人： Xiao Charles Yang

发明人： Xiao Charles Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/30608 ,  G02B26/0833

摘要： A method for forming a standoff structure for packaging devices, e.g., optical devices, integrated circuit devices. The method includes providing a substrate, e.g., silicon wafer. The substrate includes a first surface region, a second surface region, and a thickness defined between the first surface region and the second surface region. The method includes protecting selected portions of the first surface region using a masking layer while leaving a plurality of unprotected regions. Preferably, each of the unprotected regions is to be associated with an opening through the thickness of the substrate. The method causes removal of the plurality of unprotected regions to form a plurality of openings through the thickness of the substrate to provide a resulting patterned substrate. Each of the openings is bordered by a portion of the selected portions of the first surface region. Preferably, etching techniques, such as wet etch or dry etching, can be used, depending upon the embodiment. The method removes the masking layer via ashing or stripping. In a specific embodiment, the method further includes bonding a handle substrate to the patterned substrate. Preferably, the handle substrate is optically transparent. Each of the openings is bordered by a portion of the handle substrate to form a recessed region.

摘要翻译： 一种用于形成包装装置（例如光学装置，集成电路装置）的支架结构的方法。 该方法包括提供衬底，例如硅晶片。 基板包括第一表面区域，第二表面区域和限定在第一表面区域和第二表面区域之间的厚度。 该方法包括使用掩模层保护第一表面区域的选定部分，同时留下多个未保护区域。 优选地，每个未保护区域与通过基底的厚度的开口相关联。 该方法导致多个未保护区域的移除以形成穿过基底的厚度的多个开口，以提供所得到的图案化衬底。 每个开口由第一表面区域的所选部分的一部分界定。 优选地，根据实施例，可以使用蚀刻技术，例如湿蚀刻或干蚀刻。 该方法通过灰化或剥离除去掩蔽层。 在具体实施例中，该方法还包括将处理衬底接合到图案化衬底。 优选地，手柄基板是光学透明的。 每个开口由手柄基板的一部分界定以形成凹陷区域。

公开(公告)号：US09006878B2

公开(公告)日：2015-04-14

申请号：US12891518

申请日：2010-09-27

申请人： Xiao “Charles” Yang ,  Dongmin Chen ,  Philip Chen

发明人： Xiao “Charles” Yang ,  Dongmin Chen ,  Philip Chen

IPC分类号： H01L33/48 ,  B81C1/00 ,  H01L23/00

CPC分类号： B81C1/00873 ,  B81B2201/047 ,  H01L24/05 ,  H01L33/483 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member. The one or more bonding pads and the antistiction region are exposed while the one or more deflection devices is maintained within the portion of the cavity region.

摘要翻译： 一种多层集成光电路装置。 该器件具有包括其上的至少一个集成电路芯片的第一衬底，其具有单元区域和外围区域。 优选地，外围区域具有接合焊盘区域，其具有一个或多个接合焊盘和围绕一个或多个接合焊盘的每一个的抗静电区域。 该装置具有第二基板，其上具有至少一个或多个偏转装置，其上连接到第一基板。 至少一个或多个接合焊盘暴露在第一衬底上。 该装置具有覆盖第二基板的透明构件，同时形成空腔区域以允许一个或多个偏转装置在空腔区域的一部分内移动以形成夹层结构，该夹层结构包括第一基板的至少一部分， 第二基板和透明部件的一部分。 一个或多个接合焊盘和抗静电区域被暴露，同时一个或多个偏转装置保持在空腔区域的部分内。

公开(公告)号：US08652961B1

公开(公告)日：2014-02-18

申请号：US13164311

申请日：2011-06-20

申请人： Xiao “Charles” Yang

发明人： Xiao “Charles” Yang

IPC分类号： H01L29/84

CPC分类号： B81C1/00246 ,  B81B2207/07 ,  B81C1/00801 ,  B81C2203/0771 ,  H01L21/8221 ,  H01L27/0688

摘要： Methods and structure for adapting MEMS structures to form electrical interconnections for integrated circuits. A first portion and a second portion of the metal conductor, which can be electrically isolated within a CMOS IC device, can be etched to form an unetched portion of the metal conductor. The MEMS device can be patterned, from a MEMS layer formed overlying the metal conductor, via a plasma etching process, during which the unetched portion of the metal conductor is protected from the plasma. The metal conductor can be electrically coupled to the CMOS IC device via a conductive jumper or the like. Furthermore, the integrated CMOS-MEMS device can include a MEMS device coupled to a CMOS IC device via an electrically isolated metal conductor within the CMOS IC device. Also, the metal conductor can be electrically coupled to the substrate of the CMOS IC device via a conductive jumper.

摘要翻译： 用于适应MEMS结构以形成用于集成电路的电互连的方法和结构。 金属导体的可以在CMOS IC器件内电隔离的第一部分和第二部分可被蚀刻以形成金属导体的未蚀刻部分。 MEMS器件可以通过等离子体蚀刻工艺从形成在金属导体上的MEMS层图案化，在此期间金属导体的未蚀刻部分被保护免受等离子体的影响。 金属导体可以通过导电跳线等与CMOS IC器件电耦合。 此外，集成CMOS-MEMS器件可以包括通过CMOS IC器件内的电隔离金属导体耦合到CMOS IC器件的MEMS器件。 此外，金属导体可以经由导电跳线电耦合到CMOS IC器件的衬底。

公开(公告)号：US08432005B2

公开(公告)日：2013-04-30

申请号：US13494986

申请日：2012-06-12

申请人： Xiao (Charles) Yang

发明人： Xiao (Charles) Yang

IPC分类号： H01L29/82

CPC分类号： H01L22/12 ,  B81B2201/025 ,  B81C1/0023 ,  B81C1/00246 ,  B81C2203/0145 ,  B81C2203/0735 ,  H01L22/26 ,  H01L27/0688

摘要： The present invention relates to integrating an inertial mechanical device on top of a CMOS substrate monolithically using IC-foundry compatible processes. The CMOS substrate is completed first using standard IC processes. A thick silicon layer is added on top of the CMOS. A subsequent patterning step defines a mechanical structure for inertial sensing. Finally, the mechanical device is encapsulated by a thick insulating layer at the wafer level.Comparing to the incumbent bulk or surface micromachined MEMS inertial sensors, the vertically monolithically integrated inertial sensors have smaller chip size, lower parasitics, higher sensitivity, lower power, and lower cost.

摘要翻译： 本发明涉及使用IC代工厂兼容的工艺将一个惯性机械装置整体地集成在CMOS衬底之上。 CMOS基板首先使用标准IC工艺完成。 在CMOS的顶部添加厚的硅层。 随后的图案化步骤限定了用于惯性感测的机械结构。 最后，机械装置由晶圆级的厚绝缘层封装。 与现有的体积或表面微加工MEMS惯性传感器相比，垂直单片集成的惯性传感器具有更小的芯片尺寸，更低的寄生效应，更高的灵敏度，更低的功率和更低的成本。

公开(公告)号：US08148781B2

公开(公告)日：2012-04-03

申请号：US12511002

申请日：2009-07-28

申请人： Xiao (Charles) Yang

发明人： Xiao (Charles) Yang

IPC分类号： H01L27/12 ,  H01L31/0392

CPC分类号： H01L27/0248 ,  H01L23/60 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

摘要： This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs.

摘要翻译： 本发明一般涉及集成电路芯片的保护，更具体地，涉及用于保护集成电路芯片免受静电放电的微加工抑制装置。 所提出的ESD抑制装置由导电柱分散在电介质材料中。 当发生高电压ESD脉冲时，每个支柱之间的间隙就像火花隙。 当脉冲电压达到“触发电压”时，这些间隙发生火花，产生非常低的电阻路径。 在正常工作中，由于导电柱之间的物理间隙，漏电流和电容非常低。 所提出的ESD抑制装置是使用微加工技术制造的，与芯片集成在一起。

公开(公告)号：US20100187652A1

公开(公告)日：2010-07-29

申请号：US12511002

申请日：2009-07-28

申请人： Xiao (Charles) Yang

发明人： Xiao (Charles) Yang

IPC分类号： H01L29/86

CPC分类号： H01L27/0248 ,  H01L23/60 ,  H01L24/05 ,  H01L2924/14 ,  H01L2924/00

摘要： This present invention relates in general to protection of integrated circuit chips, and more particularly, to a micromachined suppression device for protecting integrated circuit chips from electrostatic discharges. The proposed ESD suppression device consists of conductive pillars are dispersed in a dielectric material. The gaps between each pillar behave like spark gaps when a high voltage ESD pulse occurs. When the voltage of the pulse reaches the “trigger voltage” these gaps spark over, creating a very low resistance path. In normal operation, the leakage current and the capacitance is very low, due to the physical gaps between the conductive pillars. The proposed ESD suppression device is fabricated using micromachining techniques to be on-chip with device ICs.

摘要翻译： 本发明一般涉及集成电路芯片的保护，更具体地，涉及用于保护集成电路芯片免受静电放电的微加工抑制装置。 所提出的ESD抑制装置由导电柱分散在电介质材料中。 当发生高电压ESD脉冲时，每个支柱之间的间隙就像火花隙。 当脉冲电压达到“触发电压”时，这些间隙发生火花，产生非常低的电阻路径。 在正常工作中，由于导电柱之间的物理间隙，漏电流和电容非常低。 所提出的ESD抑制装置是使用微加工技术制造的，与芯片集成在一起。

公开(公告)号：US20100187580A1

公开(公告)日：2010-07-29

申请号：US12511004

申请日：2009-07-28

申请人： Xiao (Charles) Yang

发明人： Xiao (Charles) Yang

IPC分类号： H01L31/09 ,  H01L31/02

CPC分类号： H01L27/14669 ,  H01L27/14627 ,  H01L27/14685 ,  H01L27/14692

摘要： Protection for infrared sensing device, and more particularly, to a monolithically integrated uncooled infrared sensing device using IC foundry compatible processes. The proposed infrared sensing device is fabricated on a completed IC substrate. In an embodiment, the infrared sensing device has a single crystal silicon plate with an absorbing layer supported a pair of springs. The absorbing layer absorbs infrared radiation and heats up the underlying silicon layer. As a result, an n well in the silicon layer changes its resistance related to its temperature coefficient of resistance (TCR). In another embodiment, the infrared sensing device has a top sensing plate supported by an underlying spring structures. The top sensing plate has sensing materials such as amorphous silicon, poly silicon, SiC, SiGe, Vanadium oxide, or YbaCuO. Finally, a micro lens array is placed on top of the sensing pixel array with a gap in between. In an embodiment, the micro lens array is fabricated on a silicon substrate and bonded to the sensing pixel array substrate. In another embodiment, the micro lens array is fabricated monolithically using amorphous silicon. The micro lens array layer encapsulates the pixel sensing array hermetically, preferably in a vacuum environment.

摘要翻译： 用于红外感测装置的保护，更具体地说，涉及使用IC代工厂兼容工艺的单片集成非制冷红外感测装置。 所提出的红外感测装置在完整的IC衬底上制造。 在一个实施例中，红外感测装置具有单晶硅板，其中吸收层支撑一对弹簧。 吸收层吸收红外辐射并加热下面的硅层。 结果，硅层中的n阱改变其与其温度电阻系数（TCR）相关的电阻。 在另一个实施例中，红外感测装置具有由下面的弹簧结构支撑的顶部感测板。 顶部感测板具有非晶硅，多晶硅，SiC，SiGe，氧化钒或YbaCuO等感测材料。 最后，微透镜阵列放置在感测像素阵列的顶部，其间有间隙。 在一个实施例中，微透镜阵列制造在硅衬底上并结合到感测像素阵列衬底。 在另一个实施例中，微透镜阵列使用非晶硅单片制造。 微透镜阵列层优选地在真空环境中封装像素感测阵列。

公开(公告)号：US20100164025A1

公开(公告)日：2010-07-01

申请号：US12490292

申请日：2009-06-23

申请人： Xiao(Charles) Yang

发明人： Xiao(Charles) Yang

IPC分类号： H01L29/84

CPC分类号： B81C1/00246 ,  B81B2201/0257 ,  H04R19/005 ,  H04R2201/003

摘要： A monolithically integrated MEMS and CMOS substrates provided by an IC-foundry compatible process. The CMOS substrate is completed first using standard IC processes. A diaphragm with stress relief corrugated structure is then fabricated on top of the CMOS. Air vent holes are then etched in the CMOS substrate. Finally, the microphone device is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated microphone that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost. Using this architecture and fabrication flow, it is feasible and cost-effective to make an array of Silicon microphones for noise cancellation, beam forming, better directionality and fidelity.

摘要翻译： 由IC-Foundry兼容工艺提供的单片集成MEMS和CMOS衬底。 CMOS基板首先使用标准IC工艺完成。 然后在CMOS的顶部制造具有应力消除波纹结构的隔膜。 然后在CMOS衬底中蚀刻通气孔。 最后，麦克风设备被晶片级的厚绝缘层封装。 采用IC代工兼容工艺的单片式麦克风产生最高的性能，最小的外形尺寸和最低的成本。 使用这种架构和制造流程，制造用于噪声消除，波束形成，更好的方向性和保真度的硅麦克风阵列是可行和成本有效的。

公开(公告)号：US07344956B2

公开(公告)日：2008-03-18

申请号：US11008483

申请日：2004-12-08

申请人： Xiao “Charles” Yang ,  Dongmin Chen ,  Philip Chen

发明人： Xiao “Charles” Yang ,  Dongmin Chen ,  Philip Chen

IPC分类号： H01L21/76

CPC分类号： B81C1/00873 ,  B81B2201/047 ,  H01L24/05 ,  H01L33/483 ,  H01L2224/04042 ,  H01L2224/48463 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00

摘要： A multilayered integrated optical and circuit device. The device has a first substrate comprising at least one integrated circuit chip thereon, which has a cell region and a peripheral region. Preferably, the peripheral region has a bonding pad region, which has one or more bonding pads and an antistiction region surrounding each of the one or more bonding pads. The device has a second substrate with at least one or more deflection devices thereon coupled to the first substrate. At least one or more bonding pads are exposed on the first substrate. The device has a transparent member overlying the second substrate while forming a cavity region to allow the one or more deflection devices to move within a portion of the cavity region to form a sandwich structure including at least a portion of the first substrate, a portion of the second substrate, and a portion of the transparent member. The one or more bonding pads and the antistiction region are exposed while the one or more deflection devices is maintained within the portion of the cavity region.

摘要翻译： 一种多层集成光电路装置。 该器件具有包括其上的至少一个集成电路芯片的第一衬底，其具有单元区域和外围区域。 优选地，外围区域具有接合焊盘区域，其具有一个或多个接合焊盘和围绕一个或多个接合焊盘的每一个的抗静电区域。 该装置具有第二基板，其上具有至少一个或多个偏转装置，其上连接到第一基板。 至少一个或多个接合焊盘暴露在第一衬底上。 该装置具有覆盖第二基板的透明构件，同时形成空腔区域以允许一个或多个偏转装置在空腔区域的一部分内移动以形成夹层结构，该夹层结构包括第一基板的至少一部分， 第二基板和透明部件的一部分。 一个或多个接合焊盘和抗静电区域被暴露，同时一个或多个偏转装置保持在空腔区域的部分内。