公开(公告)号：US08598636B2

公开(公告)日：2013-12-03

申请号：US13582624

申请日：2011-08-17

Applicant: Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

Inventor： Ru Huang ,  Xin Huang ,  Shoubin Xue ,  Yujie Ai

IPC: H01L29/80

CPC classification number: H01L23/38 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.

Abstract translation: 本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。 散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。 在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线 漏极端子相对于漏极端子施加低电位。 在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是 相对于源极端子施加较低的电位。 通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此 在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

公开(公告)号：US08563370B2

公开(公告)日：2013-10-22

申请号：US13384215

申请日：2011-07-04

Applicant: Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

Inventor： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC: H01L21/338

CPC classification number: H01L29/78696 ,  H01L21/76289 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772

Abstract: A method for fabricating a surrounding-gate silicon nanowire transistor with air sidewalls is provided. The method is compatible with the CMOS process; the introduced air sidewalls can reduce the parasitic capacitance effectively and increase the transient response characteristic of the device, thus being applicable to a high-performance logic circuit.

Abstract translation: 提供了一种制造具有空气侧壁的环形栅极硅纳米线晶体管的方法。 该方法与CMOS工艺兼容; 引入的空气侧壁可以有效地减小寄生电容并增加器件的瞬态响应特性，从而适用于高性能逻辑电路。

公开(公告)号：US20130017654A1

公开(公告)日：2013-01-17

申请号：US13266791

申请日：2011-07-15

Applicant: Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

Inventor： Ru Huang ,  Jing Zhuge ,  Jiewen Fan ,  Yujie Ai ,  Runsheng Wang ,  Xin Huang

IPC: H01L21/336 ,  B82Y99/00

CPC classification number: H01L29/66439 ,  B82Y10/00 ,  H01L29/775

Abstract: The invention discloses a fabrication method for a surrounding gate silicon nanowire transistor with air as spacers. The method comprises: performing isolation, and depositing a material A which has a higher etch selectivity ratio with respect to Si; performing photolithography to define a Fin hard mask; etching the material A to form the Fin hard mask; performing source and drain implantation; performing photolithography to define a channel region and large source/drain regions; forming the Si Fin and the large source/drains; removing the hard mask of the material A; forming a nanowire; etching the SiO2 to form a floating nanowire; forming a gate oxide layer; depositing a polysilicon; performing polysilicon injection; performing annealing to activate dopants; etching the polysilicon; depositing SiN; performing photolithography to define a gate pattern; etching the SiN and the polysilicon to form the gate pattern; separating the gate and the source/drain with a space in between filled with air; depositing SiO2 to form air sidewalls; performing annealing to densify the SiO2 layer; using subsequent processes to complete the device fabrication. The invention is compatible with the CMOS process flow. The introduction of the air sidewalls can effectively reduce the parasitic capacitance of the device, and improve the transient response of the device, so that the method is applicable for a logic circuit with high performance.

Abstract translation: 本发明公开了一种具有空气作为间隔物的周围栅极硅纳米线晶体管的制造方法。 该方法包括：执行隔离和沉积相对于Si具有较高蚀刻选择比的材料A; 执行光刻以限定Fin硬掩模; 蚀刻材料A以形成Fin硬掩模; 进行源极和漏极植入; 执行光刻以限定沟道区和大的源极/漏极区; 形成Si Fin和大源/排水; 去除材料A的硬掩模; 形成纳米线; 蚀刻SiO 2以形成浮动的纳米线; 形成栅氧化层; 沉积多晶硅; 执行多晶硅注入; 执行退火以激活掺杂剂; 蚀刻多晶硅; 沉积SiN; 执行光刻以限定栅极图案; 蚀刻SiN和多晶硅以形成栅极图案; 分离门和源/排水管之间的空间填充空气之间; 沉积SiO 2以形成空气侧壁; 进行退火以使SiO 2层致密化; 使用后续过程来完成器件制造。 本发明与CMOS工艺流程兼容。 空气侧壁的引入可以有效降低器件的寄生电容，提高器件的瞬态响应，使其适用于具有高性能的逻辑电路。

公开(公告)号：US20120302027A1

公开(公告)日：2012-11-29

申请号：US13511123

申请日：2011-11-18

Applicant: Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

Inventor： Ru Huang ,  Jiewen Fan ,  Yujie Ai ,  Shuai Sun ,  Runsheng Wang ,  Jibin Zou ,  Xin Huang

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/66772 ,  H01L29/42392 ,  H01L29/78696

Abstract: Disclosed herein is a method for fabricating a silicon nanowire field effect transistor based on a wet etching. The method includes defining an active region; depositing a silicon oxide film as a hard mask, forming a pattern of a source and a drain and a fine bar connecting the source and the drain; transferring the pattern on the hard mask to a silicon substrate by performing etching process for the silicon substrate; performing ion implanting; etching the silicon substrate by wet etching, so that the silicon fine bar connecting the source and the drain is suspended; reducing the silicon fine bar to a nano size to form a silicon nanowire; depositing a polysilicon film; forming a polysilicon gate line acrossing the silicon nanowire by electron beam lithography and forming a structure of nanowire-all-around; forming a silicon oxide sidewall at both sides of the polysilicon gate line, by depositing a silicon oxide film and subsequently etching the silicon oxide film; forming the source and the drain by using ion implantation and high temperature annealing, so that the silicon nanowire field effect transistor is finally fabricated. The method is compatible with a conventional integrated circuit fabrication technology. The fabrication process is simple and convenient, and has a short cycle.

Abstract translation: 本文公开了一种基于湿蚀刻制造硅纳米线场效应晶体管的方法。 该方法包括定义活动区域; 沉积氧化硅膜作为硬掩模，形成源极和漏极的图案以及连接源极和漏极的细棒; 通过对硅衬底进行蚀刻处理，将硬掩模上的图案转移到硅衬底; 进行离子注入; 通过湿蚀刻蚀刻硅衬底，使得连接源极和漏极的硅细棒悬空; 将硅细棒还原成纳米尺寸以形成硅纳米线; 沉积多晶硅膜; 通过电子束光刻形成跨越硅纳米线的多晶硅栅极线，并形成全纳米线的结构; 在多晶硅栅极线的两侧形成硅氧化物侧壁，通过沉积氧化硅膜并随后蚀刻氧化硅膜; 通过离子注入和高温退火形成源极和漏极，从而最终制造出硅纳米线场效应晶体管。 该方法与传统的集成电路制造技术相兼容。 制造工艺简单方便，循环周期短。

公开(公告)号：US20120168770A1

公开(公告)日：2012-07-05

申请号：US13391270

申请日：2011-11-18

Applicant: Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

Inventor： Ru Huang ,  Xin Huang ,  Tianwei Zhang ,  Qianqian Huang ,  Shiqiang Qin

IPC: H01L29/20 ,  H01L29/12

CPC classification number: H01L23/38 ,  H01L23/3738 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A heat dissipation structure of a chip in the field of microelectronics is provided. The heat dissipation structure includes a P-type superlattice layer and an N-type superlattice layer formed over an upper surface of the chip by oxidation isolation. The P-type superlattice and the N-type superlattice are isolated by silicon oxide. Through a contact hole the P-type superlattice is electrically connected to a metal layer that is applied with a low potential in the chip, and a metal layer to be connected with an external power source is formed over the P-type superlattice. Through a contact hole the N-type superlattice is electrically connected to a metal layer that is applied with a high-potential power source in the chip, and a metal layer to be connected with an external power source is formed over the N-type superlattice. The potential of the external power source connected with the P-type superlattice is lower than that of the external power source connected with the N-type superlattice. The present invention can achieve heat dissipation of the chip and meanwhile prevent the ambient heat from transferring into the chip, by using the feature that the superlattice has a low thermal conductivity and phonon-localization-like behavior.

Abstract translation: 提供了微电子领域的芯片的散热结构。 散热结构包括通过氧化隔离在芯片的上表面上形成的P型超晶格层和N型超晶格层。 P型超晶格和N型超晶格被氧化硅隔离。 通过接触孔，P型超晶格与在芯片中施加低电位的金属层电连接，并且在P型超晶格上形成与外部电源连接的金属层。 通过接触孔，N型超晶格电连接到在芯片中施加高电位电源的金属层，并且在N型超晶格上形成与外部电源连接的金属层 。 与P型超晶格连接的外部电源的电位低于与N型超晶格连接的外部电源的电位。 本发明可以实现芯片的散热，同时通过使用超晶格具有低导热性和声子定位的特性的特征，同时防止环境热量转移到芯片中。

公开(公告)号：US20120094704A1

公开(公告)日：2012-04-19

申请号：US13338201

申请日：2011-12-27

Applicant: Shukun WANG ,  Dingzhang DAI ,  Xin HUANG ,  Boya LV

Inventor： Shukun WANG ,  Dingzhang DAI ,  Xin HUANG ,  Boya LV

IPC: H04W52/04 ,  H04W72/04 ,  H04B7/26

CPC classification number: H04W72/0406 ,  H04L25/00 ,  H04W52/367

Abstract: A method and a communications system are provided. The system includes a Node B and a RNC. The Node B report the RNC whether the base station an E-DPCCH power boost capability. The RNC is also informed whether a UE supports and E-DPCCH power boost capability. If the Node B and the UE both support the E-DPCCH power boost capability, the RNC configures the resource for the Node B to perform channel estimation by using the E-DPCCH power boost feature for the UE. Through the solution of the system, the accuracy of channel estimation can be improved and thus a bit error rate in high-speed data transmission can be reduced.

Abstract translation: 提供了一种方法和通信系统。 该系统包括节点B和RNC。 节点B向RNC报告基站是否具有E-DPCCH功率提升能力。 RNC还通知UE是否支持和E-DPCCH功率提升能力。 如果节点B和UE都支持E-DPCCH功率提升能力，则RNC通过使用UE的E-DPCCH功率提升特性来配置节点B的资源来进行信道估计。 通过系统的解决方案，可以提高信道估计的准确性，从而可以降低高速数据传输中的误码率。

公开(公告)号：US20120071515A1

公开(公告)日：2012-03-22

申请号：US13126907

申请日：2009-10-27

Applicant: Shangjin Yang ,  Jianhui Yan ,  Ligang Wang ,  Xingna Guo ,  Shubin Li ,  Guoqiang Wu ,  Ruiya Zuo ,  Xin Huang ,  Hongtao Wang ,  Lingling Wang ,  Wenjuan Huang ,  Huigang Lu ,  Ke Feng ,  Fang Li ,  Huimin He ,  Yu Liu

Inventor： Shangjin Yang ,  Jianhui Yan ,  Ligang Wang ,  Xingna Guo ,  Shubin Li ,  Guoqiang Wu ,  Ruiya Zuo ,  Xin Huang ,  Hongtao Wang ,  Lingling Wang ,  Wenjuan Huang ,  Huigang Lu ,  Ke Feng ,  Fang Li ,  Huimin He ,  Yu Liu

IPC: A61K31/4427 ,  A61P35/00 ,  C07D401/04

CPC classification number: C07D401/04 ,  C07D213/60 ,  C07D213/61 ,  C07D213/73

Abstract: The present invention discloses a nitropyridinyl ethyleneimine compound as shown in the formula I and a preparation method of the same, as well as use of the compound in manufacture of a prodrug and in manufacture of a drug for treating a tumor.

Abstract translation: 本发明公开了式I所示的硝基吡啶基亚乙基亚胺化合物及其制备方法，以及该化合物在制备前体药物和制备用于治疗肿瘤的药物中的用途。

公开(公告)号：US08129114B2

公开(公告)日：2012-03-06

申请号：US11990713

申请日：2006-08-24

Applicant: Shirin K. Ford ,  Edwin A. Clark ,  Xin Huang

Inventor： Shirin K. Ford ,  Edwin A. Clark ,  Xin Huang

IPC: C12Q1/68 ,  G01N33/574 ,  A61K39/395

CPC classification number: C12Q1/6886 ,  C12Q2600/106 ,  C12Q2600/136 ,  G01N33/57419 ,  G01N2333/485 ,  G01N2333/70596 ,  G01N2333/71 ,  G01N2800/52

Abstract: EGFR biomarkers useful in a method for predicting the likelihood that a mammal that will respond therapeutically to a method of treating cancer comprising administering an EGFR modulator, wherein the method comprises (a) measuring in the mammal the level of at least one biomarker selected from epiregulin and amphiregulin, (b) exposing a biological sample from the mammal to the EGFR modulator, and (c) following the exposing of step (b), measuring in the biological sample the level of the at least one biomarker, wherein an increase in the level of the at least one biomarker measured in step (c) compared to the level of the at least one biomarker measured in step (a) indicates an increased likelihood that the mammal will respond therapeutically to the method of treating cancer.

Abstract translation: EGFR生物标志物可用于预测将对治疗癌症治疗的治疗反应的哺乳动物的可能性的方法，其包括施用EGFR调节剂，其中所述方法包括（a）在哺乳动物中测量至少一种选自上皮蛋白的生物标志物 （b）将生物样品从哺乳动物暴露于EGFR调节剂，和（c）在暴露步骤（b）之后，在生物样品中测量至少一种生物标志物的水平，其中增加 与步骤（a）中测量的至少一种生物标志物的水平相比，在步骤（c）中测量的至少一种生物标志物的水平表明哺乳动物对治疗癌症的方法治疗反应的可能性增加。

公开(公告)号：US08028031B2

公开(公告)日：2011-09-27

申请号：US12147490

申请日：2008-06-27

Applicant: Ryan Colvin ,  Chad Mills ,  Robert McCann ,  Geoff Hulten ,  Harry Katz ,  Eriola Kruja ,  Xin Huang ,  Joshua Korb

Inventor： Ryan Colvin ,  Chad Mills ,  Robert McCann ,  Geoff Hulten ,  Harry Katz ,  Eriola Kruja ,  Xin Huang ,  Joshua Korb

IPC: G06F15/16 ,  G06F12/00

CPC classification number: G06Q10/107 ,  H04L51/12

Abstract: Determining email filtering type based on sender classification. Incoming email is accessed and a sender of the incoming email is identified. The reputation of the sender of the incoming email is determined. An email sender classification is made based on the reputation of the sender. A determination of the type of filtering operations to be performed by an email filter on the email is made based on the classification. The parameters of the type of filtering operations to be performed are determined. The parameters of the type of filtering operations to be performed are provided to the email filter.

Abstract translation: 根据发送者分类确定电子邮件过滤类型。 访问收到的电子邮件，并确定收到的电子邮件的发件人。 确定传入电子邮件的发件人的声誉。 电子邮件发送者分类是根据发信人的声誉进行的。 基于分类确定由电子邮件过滤器执行的过滤操作的类型。 确定要执行的过滤操作的类型的参数。 将要执行的过滤操作的类型的参数提供给电子邮件过滤器。

公开(公告)号：US07768804B2

公开(公告)日：2010-08-03

申请号：US12344273

申请日：2008-12-25

Applicant: Chang-Xin Huang

Inventor： Chang-Xin Huang

IPC: H02M1/12

CPC classification number: H02M7/5395 ,  H05B41/2822 ,  H05B41/3927

Abstract: An inverter includes a counter, a PWM generator, a central controller and a power converter. The counter is used for receiving a frame switch signal to generate a frame counting signal. The PWM generator is coupled to the counter, and is used to select a specific frequency among a plurality of predetermined frequencies according to the frame counting signal, and generate a modulated signal having the specific frequency. The central controller is coupled to the PWM generator, and is used to generate a processed signal according to the modulated signal. The power converter is coupled to the central controller, and is used to generate an output signal according to the processed signal.

Abstract translation: 逆变器包括计数器，PWM发生器，中央控制器和功率转换器。 计数器用于接收帧切换信号以产生帧计数信号。 PWM发生器耦合到计数器，并且用于根据帧计数信号在多个预定频率中选择特定频率，并且生成具有特定频率的调制信号。 中央控制器耦合到PWM发生器，并用于根据调制信号产生处理信号。 功率转换器耦合到中央控制器，并用于根据处理的信号产​​生输出信号。