公开(公告)号：US20100082882A1

公开(公告)日：2010-04-01

申请号：US12338527

申请日：2008-12-18

Applicant: Kwang-Seok Im ,  Bum-Seok Yu ,  Yang-sup Lee

Inventor： Kwang-Seok Im ,  Bum-Seok Yu ,  Yang-sup Lee

IPC: G06F12/02 ,  G06F12/00

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A computing system includes a host, a data source device, and a controller. The controller is configured to respond to a random access command from the host by setting information in a register that selects what data is to be accessed in the data source device. The controller then successively accesses the data in the data source device using the information that was set in the register.

Abstract translation: 计算系统包括主机，数据源设备和控制器。 控制器被配置为通过设置在数据源设备中选择要访问的数据的寄存器中的信息来响应来自主机的随机访问命令。 然后，控制器使用在寄存器中设置的信息连续地访问数据源设备中的数据。

公开(公告)号：US20080189490A1

公开(公告)日：2008-08-07

申请号：US11833750

申请日：2007-08-03

Applicant: Won-Moon Cheon ,  Yang-Sup Lee

Inventor： Won-Moon Cheon ,  Yang-Sup Lee

IPC: G06F13/00

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: A system and method for memory mapping are provided, the system including a logical unit to physical unit map table, data unit groups in signal communication with the map table, and log unit groups, each associated with a corresponding one of the data unit groups, where updated data for any data unit within one of the data unit groups is stored in any log unit within the corresponding one of the log unit groups, and the method including receiving write data for a logical unit number from a host determining which of a plurality of data block groups comprises the logical unit number, and storing the write data in any unfilled log unit of a log block group corresponding to the determined data block group.

Abstract translation: 提供了一种用于存储器映射的系统和方法，该系统包括到物理单元映射表的逻辑单元，与映射表信号通信的数据单元组以及每个与对应的数据单元组相关联的日志单元组， 其中在所述数据单元组之一内的任何数据单元的更新数据被存储在所述对应单元组中的相应一个中的任何日志单元中，并且所述方法包括从主机接收用于逻辑单元号的写入数据，所述主机确定多个 的数据块组包括逻辑单元号，并将写入数据存储在对应于所确定的数据块组的日志块组的任何未填充日志单元中。

公开(公告)号：US20080155317A1

公开(公告)日：2008-06-26

申请号：US11606900

申请日：2006-12-01

Applicant: Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

Inventor： Jin-Hyuk Kim ,  Yang-Sup Lee ,  Young-Gon Kim

IPC: G06F11/00

CPC classification number: G11C29/76 ,  G06F12/0246 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7204

Abstract: An apparatus, memory device controller and method of controlling a memory device are provided. The example apparatus may include a bad block bitmap referencing unit configured to obtain bad block information from a bad block bitmap based on a given memory address, the given memory address being one of a logical memory address and a physical memory address corresponding to the logical memory address, the bad block information indicating whether a given memory block corresponding to the given memory address is a bad block and a memory mapping unit configured to obtain the physical memory address corresponding to the logical memory address, and configured to obtain a reserved physical memory address corresponding to the physical memory address if the bad block information indicates that the given memory block is a bad block. In an example, the apparatus may be embodied as a memory device controller including a flash translation layer (FTL).

Abstract translation: 提供了一种设备，存储器件控制器和控制存储器件的方法。 该示例设备可以包括坏块位图参考单元，其被配置为基于给定的存储器地址从坏块位图获得坏块信息，给定存储器地址是与逻辑存储器对应的逻辑存储器地址之一和物理存储器地址 指示与给定存储器地址相对应的给定存储块是否为坏块的坏块信息和被配置为获得与逻辑存储器地址对应的物理存储器地址的存储器映射单元，并且被配置为获得预留的物理存储器地址 对应于物理存储器地址，如果坏块信息指示给定的存储器块是坏块。 在一个示例中，该装置可以被实现为包括闪存转换层（FTL）的存储器件控制器。

公开(公告)号：US09239780B2

公开(公告)日：2016-01-19

申请号：US13613443

申请日：2012-09-13

Applicant: Gyu-Dong Shim ,  Yang-Sup Lee ,  Won-Moon Cheon

Inventor： Gyu-Dong Shim ,  Yang-Sup Lee ,  Won-Moon Cheon

IPC: G06F12/00 ,  G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7205

Abstract: Memory blocks of a nonvolatile memory device are managed by identifying a full memory block, determining whether a block life of the full memory block exceeds a threshold value, and upon determining that the block life of the full memory block exceeds the threshold value, selecting the full memory block as a target block for garbage collection. The threshold of the block life is determined using an average write distance of logical pages programmed in the nonvolatile memory device.

Abstract translation: 非易失性存储器件的存储器块通过识别完整存储器块，确定整个存储器块的块寿命是否超过阈值来管理，并且在确定完整存储器块的块寿命超过阈值时，选择 完全内存块作为垃圾收集的目标块。 使用在非易失性存储器件中编程的逻辑页面的平均写入距离来确定块寿命的阈值。

公开(公告)号：US08760918B2

公开(公告)日：2014-06-24

申请号：US13137423

申请日：2011-08-15

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

公开(公告)号：US08335886B2

公开(公告)日：2012-12-18

申请号：US12534358

申请日：2009-08-03

Applicant: Yang-sup Lee

Inventor： Yang-sup Lee

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C11/5621 ,  G06F12/0246 ,  G06F2212/7211 ,  G11C16/349 ,  G11C2211/5641

Abstract: A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation.

Abstract translation: 公开了一种在包括单层存储器单元块（SLC）和多级存储器单元块（MLC）的非易失性存储器内执行损耗均衡操作的方法。 该方法包括相对于应用于逻辑块地址（LBA）的编程/擦除（P / E）操作的数量来计算平均擦除点，相对于应用的P / E操作的数量，SLC模式使用点 相对于应用于MLC的P / E操作的数量以及相对于平均擦除点，SLC模式使用点和MLC模式使用点的损耗值，SLC，MLC模式使用点; 然后如果磨损值超过限定的阈值，则进行磨损均衡操作。

公开(公告)号：US08214582B2

公开(公告)日：2012-07-03

申请号：US12711461

申请日：2010-02-24

Applicant: Yang-sup Lee ,  Prakash Talawar ,  Chan-ik Park

Inventor： Yang-sup Lee ,  Prakash Talawar ,  Chan-ik Park

IPC: G06F13/00 ,  G11C5/06

CPC classification number: G06F3/0643 ,  G06F3/0613 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0679 ,  G06F3/068 ,  G06F12/0246 ,  G06F2212/7202 ,  G06F2212/7211 ,  G11C2211/5641

Abstract: Provided is a system storing data received from an application or file system in a non-volatile memory system of single-level cells and multi-level cells in accordance with one or more data characteristics. The non-volatile memory system includes a non-volatile memory cell array having a plurality of multi-level cells forming a MLC area and a plurality of single-level cells forming a SLC area, and an interface unit analyzing a characteristic of the write data and generating a corresponding data characteristic signal. A flash transition layer receives the data characteristic signal, and determines whether the write data should be stored in the MLC area or the SLC area based on whether or not the write data will be accessed by the file, or whether the address associated with the write data is frequently updated or not.

Abstract translation: 提供了一种系统，其根据一个或多个数据特征将从应用或文件系统接收的数据存储在单级单元和多级单元的非易失性存储器系统中。 非易失性存储器系统包括具有形成MLC区域的多个多电平单元和形成SLC区域的多个单电平单元的非易失性存储单元阵列，以及分析写入数据的特性的接口单元 并产生相应的数据特征信号。 闪速转换层接收数据特征信号，并且基于写入数据是否被文件访问来确定写入数据是否应存储在MLC区域或SLC区域中，或者是否与写入相关联的地址 数据频繁更新。

公开(公告)号：US08027194B2

公开(公告)日：2011-09-27

申请号：US12457485

申请日：2009-06-12

Applicant: Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

Inventor： Jaesoo Lee ,  Kangho Roh ,  Wonhee Cho ,  Hojun Shim ,  Youngjoon Choi ,  Jaehoon Heo ,  Je-Hyuck Song ,  Seung-Duk Cho ,  Seontaek Kim ,  Moonwook Oh ,  Jong Tae Park ,  Wonmoon Cheon ,  Chanik Park ,  Yang-sup Lee

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3431 ,  G11C29/00 ,  G11C2211/5621 ,  Y02D10/13

Abstract: One embodiment of a nonvolatile memory device includes a memory cell array including a plurality of multi-level cells, and a control unit configured to determine a characteristic of data to be stored in the memory cell array. The control unit is configured to select one of plural multi-bit programming methods based on the determination. Data is stored in the memory cell array according to the selected multi-bit programming method, and at least one of the plural multi-bit programming methods maintains least significant bit data when there is a program fail of most significant bit data.

Abstract translation: 非易失性存储器件的一个实施例包括包括多个多电平单元的存储单元阵列，以及配置为确定要存储在存储单元阵列中的数据的特性的控制单元。 控制单元被配置为基于该确定来选择多个多位编程方法之一。 数据根据所选择的多位编程方法存储在存储单元阵列中，并且当存在最高有效位数据的程序失败时，多个多位编程方法中的至少一个保持最低有效位数据。

公开(公告)号：US20110026326A1

公开(公告)日：2011-02-03

申请号：US12897869

申请日：2010-10-05

Applicant: Kyoong-Han LEE ,  Young-Joon CHOI ,  Yang-Sup LEE

Inventor： Kyoong-Han LEE ,  Young-Joon CHOI ,  Yang-Sup LEE

IPC: G11C16/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G11C16/04 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2229/723

Abstract: A method for operating a memory system including a flash memory device having a plurality of memory blocks includes determining whether a read error generated during a read operation of the flash memory device is caused by read disturbance and replacing a memory block which includes the read error, with a spare memory block if the read error is caused by read disturbance.

Abstract translation: 一种用于操作包括具有多个存储器块的闪速存储器件的存储器系统的方法，包括：确定在闪速存储器件的读取操作期间产生的读取错误是否由读取干扰引起，并且更换包括读取错误的存储器块， 如果读取错误是由读取干扰引起的，则会带有备用存储器块。

公开(公告)号：US07797481B2

公开(公告)日：2010-09-14

申请号：US11771531

申请日：2007-06-29

Applicant: Yang-Sup Lee ,  Chan-Ik Park ,  Won-Moon Cheon

Inventor： Yang-Sup Lee ,  Chan-Ik Park ,  Won-Moon Cheon

IPC: G06F12/16

CPC classification number: G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

Abstract: A memory system and corresponding method of wear-leveling are provided, the system including a controller, a random access memory in signal communication with the controller, and another memory in signal communication with the controller, the other memory comprising a plurality of groups, each group comprising a plurality of first erase units or blocks and a plurality of second blocks, wherein the controller exchanges a first block from a group with a second block in response to at least one block erase count within the group; and the method including receiving a command having a logical address, converting the logical address into a logical block number, determining a group number for a group that includes the converted logical block number, and checking whether group information comprising block erase counts for the group is loaded into random access memory, and if not, loading the group information into random access memory.

Abstract translation: 提供了一种存储器系统和相应的磨损均衡方法，所述系统包括控制器，与控制器进行信号通信的随机存取存储器，以及与控制器进行信号通信的另一存储器，所述另一存储器包括多个组，每个组 组包括多个第一擦除单元或块和多个第二块，其中响应于该组内的至少一个块擦除计数，控制器从具有第二块的组与第一块交换第一块; 所述方法包括：接收具有逻辑地址的命令，将所述逻辑地址转换为逻辑块号，确定包含所转换的逻辑块号的组的组号，以及检查是否包括所述组的块擦除计数的组信息是 加载到随机存取存储器中，如果没有，将组信息加载到随机存取存储器中。