公开(公告)号：US06713821B2

公开(公告)日：2004-03-30

申请号：US10155619

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Mu-Yi Liu ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L31062

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A mask ROM device is described. The mask ROM device includes a substrate, a gate, a double diffused source/drain region that comprises a first doped region and a second doped region, a channel region, a coding region, a dielectric layer and a word line. The gate is disposed on the substrate. The double diffused source/drain region is positioned beside the sides of the gate in the substrate, wherein the second doped region is located at the periphery of the first doped region in the substrate. The channel region is located between the double diffused source/drain region in the substrate. The coding region is disposed in the substrate at the intersection between the sides of the channel region and the double diffused source/drain region. The dielectric layer is disposed above the double diffused source/drain region, while the word line is disposed above the dielectric layer and the gate.

摘要翻译： 描述掩模ROM设备。 掩模ROM器件包括衬底，栅极，包括第一掺杂区域和第二掺杂区域的双扩散源极/漏极区域，沟道区域，编码区域，电介质层和字线。 栅极设置在基板上。 双扩散源极/漏极区域位于衬底中的栅极的侧面旁边，其中第二掺杂区域位于衬底中的第一掺杂区域的外围。 沟道区位于衬底中的双扩散源极/漏极区之间。 编码区域设置在沟道区域和双扩散源极/漏极区域的相交处的衬底中。 电介质层设置在双扩散源极/漏极区域的上方，而字线设置在电介质层和栅极之上。

公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L2994

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

摘要翻译： 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

公开(公告)号：US06482706B1

公开(公告)日：2002-11-19

申请号：US10013982

申请日：2001-12-10

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned conductive layer is used as a mask for forming a pocket doped region. A spacer is formed on a side-wall of the conductive layer. As the implantation region is confined by the side-wall, a buried drain region formed by drain implantation is reduced. Therefore, the effective channel length is not reduced due to the diffusion of the buried drain region. It is thus advantageous to scale down device dimension.

摘要翻译： 一种使用间隔物来缩小器件尺寸以限制掩埋漏极注入的方法，适用于形成诸如衬底/氧化物/氮化物/氧化物/硅（SONOS）堆叠器件或氮化物只读存储器（NROM）器件的存储器件。 使用图案化导电层作为形成口袋掺杂区域的掩模。 在导电层的侧壁上形成间隔物。 当注入区被侧壁限制时，通过漏极注入形成的掩埋漏极区减小。 因此，由于埋漏区的扩散，有效沟道长度不会降低。 因此有利的是缩小器件尺寸。

公开(公告)号：US06458642B1

公开(公告)日：2002-10-01

申请号：US09990159

申请日：2001-11-20

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L218238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method of fabricating a SONOS device, in which a first silicon oxide layer, a trapping layer, and a second silicon oxide layer are formed on the substrate. Then, a mask pattern is formed over the substrate to serve as a mask in the implantation process for forming the buried bit-lines. Afterward, a portion of the mask pattern is removed to increase the gap size of the mask pattern, then a pocket ion implantation is performed to form a pocket doped region at the periphery of the buried bit-line by using the mask pattern as a mask. Subsequently, the mask pattern is removed and a thermal process is conducted using the trapping layer as a mask to form a buried bit-line oxide layer. A word-line is subsequently formed over the substrate.

摘要翻译： 一种制造SONOS器件的方法，其中在衬底上形成第一氧化硅层，俘获层和第二氧化硅层。 然后，在用于形成掩埋位线的注入工艺中，在衬底上形成掩模图案以用作掩模。 之后，去除掩模图案的一部分以增加掩模图案的间隙尺寸，然后通过使用掩模图案作为掩模，进行袋离子注入以在掩埋位线的周围形成凹坑掺杂区域 。 随后，去除掩模图案，并使用捕获层作为掩模进行热处理，以形成掩埋的位线氧化物层。 随后在衬底上形成字线。

公开(公告)号：US07291870B2

公开(公告)日：2007-11-06

申请号：US10904475

申请日：2004-11-12

申请人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266 ,  H01L29/7436 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

摘要翻译： 耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

公开(公告)号：US07187527B2

公开(公告)日：2007-03-06

申请号：US10933181

申请日：2004-09-02

申请人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

摘要翻译： 用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。 有源P环围绕具有与半导体衬底相同的导电类型的导电区域的晶体管的源极和漏极。 耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。 偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

公开(公告)号：US06587387B1

公开(公告)日：2003-07-01

申请号：US10055571

申请日：2002-01-22

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C2900

CPC分类号： G11C29/025 ,  G11C17/14 ,  G11C29/02 ,  G11C2029/5006

摘要： A Mask ROM testing device is described. The Mask ROM testing device comprises a substrate, a plurality of buried bit-lines in the substrate and a plurality of word-lines on the substrate perpendicular to the buried bit-lines. Each buried bit-line has two end portions with a combined length of about 3˜30 &mgr;m and can have an N-type conductivity or a P-type conductivity.

摘要翻译： 描述了面罩ROM测试装置。 掩模ROM测试装置包括衬底，衬底中的多个掩埋位线和垂直于掩埋位线的衬底上的多个字线。 每个埋置的位线具有两个具有约3〜30μm的组合长度的端部，并且可以具有N型导电性或P型导电性。

公开(公告)号：US06440803B1

公开(公告)日：2002-08-27

申请号：US10047685

申请日：2002-01-14

申请人： Shui-Chin Huang ,  Yen-hung Yeh ,  Tso-Hung Fan ,  Chun-Yi Yang ,  Chun-Jung Lin

发明人： Shui-Chin Huang ,  Yen-hung Yeh ,  Tso-Hung Fan ,  Chun-Yi Yang ,  Chun-Jung Lin

IPC分类号： H01L218238

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A method of fabricating a mask ROM, in which conductive strips are formed with a cap layer on each of them, then a plurality of spacers are formed on the side-walls of the conductive strips, while the substrate under the spacers are used as the coding regions. The buried bit-lines are formed in the substrate between the spacers, then a two-step coding process is performed, wherein the coding regions at the first and the second side of the conductive strips are selectively doped by a first and a second tilt coding implantation with a first and a second coding mask. After the second mask layer and the cap layer are removed, a conductive layer is formed over the substrate, then the conductive layer and the conductive strips are patterned successively to form a plurality of word-lines and plural gates, respectively.

摘要翻译： 一种制造掩模ROM的方法，其中在每个掩模ROM上形成具有覆盖层的导电条，然后在导电条的侧壁上形成多个间隔物，同时使用间隔物下的基板作为 编码区域。 掩埋位线形成在间隔物之间​​的衬底中，然后进行两步编码处理，其中导电条的第一和第二侧的编码区被第一和第二倾斜编码 用第一和第二编码掩模进行植入。 在除去第二掩模层和盖层之后，在衬底上形成导电层，然后分别对导电层和导电条进行图案化以形成多个字线和多个栅极。