中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

29 records (took 0.015 seconds)

    Practical Approach to Layout Migration
    21.
    发明申请
    Practical Approach to Layout Migration 有权
    布局迁移的实践方法

    公开(公告)号：US20110161907A1

    公开(公告)日：2011-06-30

    申请号：US12647997

    申请日：2009-12-28

    Applicant: Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J.H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Ying-Chou Cheng ,  Tsong-Hua Ou ,  Josh J.H. Feng ,  Cheng-Lung Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

    Abstract: The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node.

    Abstract translation: 本公开提供了许多不同实施例中的集成电路设计方法。 一种示例性的IC设计方法包括在第一技术节点中提供电路的IC设计布局; 将电路的IC设计布局迁移到第二个技术节点; 根据电路的电气参数对迁移的IC设计布局进行电气图案化（ePatterning）修改; 然后根据第二技术节点中的电路的迁移的IC设计布局制造掩模。

    METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN
    23.
    发明申请
    METHOD, SYSTEM, AND APPARATUS FOR ADJUSTING LOCAL AND GLOBAL PATTERN DENSITY OF AN INTEGRATED CIRCUIT DESIGN 有权
    用于调整集成电路设计的局部和全局模式密度的方法，系统和装置

    公开(公告)号：US20110204470A1

    公开(公告)日：2011-08-25

    申请号：US12712665

    申请日：2010-02-25

    Applicant: Ying-Chou Cheng ,  Cheng-Lung Tsai ,  Tsong-Hua Ou ,  Cheng Kun Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Ying-Chou Cheng ,  Cheng-Lung Tsai ,  Tsong-Hua Ou ,  Cheng Kun Tsai ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: H01L23/544 ,  G06F17/50

    CPC classification number: G06F17/5068

    Abstract: An integrated circuit (IC) design method providing a circuit design layout having a plurality of functional blocks disposed a distance away from each other; identifying a local pattern density to an approximate dummy region, on the circuit design layout, within a predefined distance to one of the functional blocks; performing a local dummy insertion to the approximate dummy region according to the local pattern density; repeating the identifying and performing to at least some other of the functional blocks; and implementing a global dummy insertion to a non-local dummy region according to a global pattern density.

    Abstract translation: 一种提供电路设计布局的集成电路（IC）设计方法，其具有彼此远离设置的多个功能块; 将电路设计布局上的近似虚拟区域的局部图案密度识别在与功能块之一预定义的距离内; 根据局部图案密度对近似虚拟区进行局部虚拟插入; 重复对所述功能块中的至少一些其他功能块的识别和执行; 并且根据全局模式密度对非局部虚拟区域实施全局虚拟插入。

    TARGET-BASED DUMMY INSERTION FOR SEMICONDUCTOR DEVICES
    26.
    发明申请
    TARGET-BASED DUMMY INSERTION FOR SEMICONDUCTOR DEVICES 有权
    用于半导体器件的基于目标的DUMMY插入

    公开(公告)号：US20130061196A1

    公开(公告)日：2013-03-07

    申请号：US13227118

    申请日：2011-09-07

    Applicant: Ying-Chou Cheng ,  Boren Luo ,  Wen-Hao Liu ,  Tsong-Hua Ou ,  Chih-Wei Hsu ,  Wen-Chun Huang ,  Ru-Gun Liu

    Inventor： Ying-Chou Cheng ,  Boren Luo ,  Wen-Hao Liu ,  Tsong-Hua Ou ,  Chih-Wei Hsu ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  G06F2217/80 ,  Y02P90/265

    Abstract: The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.

    Abstract translation: 本公开提供了用于基于目标的虚拟插入的集成电路方法。 一种方法包括提供集成电路（IC）设计布局，并提供用于模拟IC设计布局热效应的热模型，热模型包括光学仿真和硅校准。 该方法还包括提供热模型和IC设计布局的卷积以产生IC设计布局的热图像轮廓，定义用于优化热图像轮廓的热均匀性的热目标，比较热目标和热图像 以确定差异数据，并且基于差异数据对IC设计布局进行热假插入以提供基于目标的IC设计布局。

    PARAMETERIZED DUMMY CELL INSERTION FOR PROCESS ENHANCEMENT
    27.
    发明申请
    PARAMETERIZED DUMMY CELL INSERTION FOR PROCESS ENHANCEMENT 有权
    用于过程增强的参数化DUMMY CELL插入

    公开(公告)号：US20120144361A1

    公开(公告)日：2012-06-07

    申请号：US12959150

    申请日：2010-12-02

    Applicant: Ying-Chou Cheng ,  Tsong-Hua Ou ,  Wen-Hao Liu ,  Ru-Gun Liu ,  Wen-Chun Huang

    Inventor： Ying-Chou Cheng ,  Tsong-Hua Ou ,  Wen-Hao Liu ,  Ru-Gun Liu ,  Wen-Chun Huang

    IPC: G06F17/50

    CPC classification number: G06F17/5068 ,  G06F2217/12 ,  G06F2217/80 ,  Y02P90/265

    Abstract: The present disclosure relates to parameterized dummy cell insertion for process enhancement and methods for fabricating the same. In accordance with one or more embodiments, methods include providing an integrated circuit (IC) design layout with defined pixel-units, simulating thermal effect to the IC design layout including each pixel-unit, generating a thermal effect map of the IC design layout including each pixel-unit, determining a target absorption value for the IC design layout, and performing thermal dummy cell insertion to each pixel-unit of the IC design layout based on the determined target absorption value.

    Abstract translation: 本公开涉及用于过程增强的参数化虚拟单元插入及其制造方法。 根据一个或多个实施例，方法包括提供具有定义的像素单元的集成电路（IC）设计布局，模拟包括每个像素单元的IC设计布局的热效应，生成IC设计布局的热效应图，包括 每个像素单元，确定IC设计布局的目标吸收值，并且基于所确定的目标吸收值，向IC设计布局的每个像素单元执行热虚拟单元插入。

    Tool organizing device
    28.
    发明申请
    Tool organizing device 审中-公开
    工具组织装置

    公开(公告)号：US20100295430A1

    公开(公告)日：2010-11-25

    申请号：US12799309

    申请日：2010-04-22

    Applicant: Ying Chou Cheng

    Inventor： Ying Chou Cheng

    IPC: A47B81/00 ,  A47B88/04 ,  A47B96/00 ,  A47B97/00

    CPC classification number: B25H3/028 ,  B25H3/04 ,  B25H3/06

    Abstract: A tool organizing device includes a housing having two side walls, a rear wall, a bottom wall, a front opening, and a peripheral fence extended from an upper wall for forming a compartment in the peripheral fence for receiving tool members, and having a number of rails for slidably attaching drawers, and having a number of apertures formed in the side walls for hooking tool members, a tray is selectively and detachably attached to the bottom wall with four posts and includes a peripheral fence extended upwardly from a board for forming a compartment above the board and within the peripheral fence and for receiving tool members, a panel is selectively attached to the housing for hooking tool members.

    Abstract translation: 工具组合装置包括具有两个侧壁的壳体，后壁，底壁，前开口和从上壁延伸的外围围栏，用于在周围围栏中形成用于接纳工具构件的隔室，并具有数量 用于可滑动地连接抽屉的轨道，并且在侧壁中形成有用于钩住工具构件的多个孔，托盘通过四个柱选择性地和可拆卸地附接到底壁，并且包括从用于形成 隔板，并且在周围围栏内，并且为了接收工具构件，面板选择性地附接到壳体以钩住工具构件。

Patent Agency Ranking