公开(公告)号：US08850366B2

公开(公告)日：2014-09-30

申请号：US13564019

申请日：2012-08-01

Applicant: Ru-Gun Liu ,  Shuo-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

Inventor： Ru-Gun Liu ,  Shuo-Yen Chou ,  Hoi-Tou Ng ,  Ken-Hsien Hsieh ,  Yi-Yin Chen

IPC: G06F17/50

CPC classification number: G03F1/36 ,  G03F1/14 ,  G03F1/144 ,  G03F7/701 ,  G03F7/70433 ,  G03F7/70441 ,  G06F17/5068

Abstract: A method for making a mask for an integrated circuit (IC) design includes receiving an IC design layout having a plurality IC features and performing a targeted-feature-surrounding (TFS) checking operation to identify a targeted-feature-surrounding-location (TFSL) in the IC design layout. The method also includes inserting a phase-bar (PB) to the TFSL, performing an optical proximity correction (OPC) to the IC design layout having the PB to form a modified IC design layout and providing the modified IC design layout for fabrication of the mask.

Abstract translation: 制造用于集成电路（IC）设计的掩模的方法包括接收具有多个IC特征的IC设计布局，并执行目标特征周围（TFS）检查操作以识别目标特征周围位置（TFSL ）在IC设计布局中。 该方法还包括将相位棒（PB）插入到TFSL中，对具有PB的IC设计布局执行光学邻近校正（OPC）以形成修改的IC设计布局，并提供修改的IC设计布局来制造 面具。

公开(公告)号：US08779592B2

公开(公告)日：2014-07-15

申请号：US13461224

申请日：2012-05-01

Applicant: Yu-Po Tang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

Inventor： Yu-Po Tang ,  Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Ru-Gun Liu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/10 ,  H01L29/74

CPC classification number: H01L21/76838 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first conductive line disposed over a substrate. The first conductive line is located in a first interconnect layer and extends along a first direction. The semiconductor device includes a second conductive line and a third conductive line each extending along a second direction different from the first direction. The second and third conductive lines are located in a second interconnect layer that is different from the first interconnect layer. The second and third conductive lines are separated by a gap that is located over or below the first conductive line. The semiconductor device includes a fourth conductive line electrically coupling the second and third conductive lines together. The fourth conductive line is located in a third interconnect layer that is different from the first interconnect layer and the second interconnect layer.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括设置在衬底上的第一导电线。 第一导线位于第一互连层中并沿着第一方向延伸。 半导体器件包括沿着与第一方向不同的第二方向延伸的第二导线和第三导线。 第二和第三导线位于与第一互连层不同的第二互连层中。 第二和第三导线被位于第一导电线之上或之下的间隙分开。 半导体器件包括将第二和第三导线电耦合在一起的第四导线。 第四导线位于与第一互连层和第二互连层不同的第三互连层中。

公开(公告)号：US08631379B2

公开(公告)日：2014-01-14

申请号：US12702591

申请日：2010-02-09

Applicant: Pi-Tsung Chen ,  Ming-Hui Chih ,  Ken-Hsien Hsieh ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yung-Sung Yen

Inventor： Pi-Tsung Chen ,  Ming-Hui Chih ,  Ken-Hsien Hsieh ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Wen-Ju Yang ,  Gwan Sin Chang ,  Yung-Sung Yen

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

Abstract translation: 本发明的各种实施例提供了确保集成电路的布局是可分割的技术。 在方法实施例中，在具有布局库作为输入的客户站点中生成布局，其中库提供已经被验证为可以吐出并且可以被使用的示例性布局以及可能引起冲突的布局。 还提供了实时奇数周期检查器，其中检查器在布局生成期间出现时实时地识别冲突区域和奇数周期。 为了减少各种设备的存储器使用布局可以被分离，使得可以针对冲突来检查每个单独布局或少量布局而不是用于整个应用电路的大布局。 一旦布局在客户现场准备就绪，就将其发送到代工厂，将其分解成两个面具并进行录制。 还公开了其他实施例。

公开(公告)号：US08631360B2

公开(公告)日：2014-01-14

申请号：US13448977

申请日：2012-04-17

Applicant: Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Yu-Po Tang ,  Chia-Ping Chiang ,  Feng-Ju Chang ,  Cheng Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F1/70

Abstract: A method for performing OPC and evaluating OPC solutions is disclosed. An exemplary method includes receiving a design database corresponding to an IC circuit mask. A first lithography simulation and evaluation is performed on the design database utilizing a first set of performance indexes. A modification is made to the design database based on a result of performing the first lithography simulation and evaluation. A second lithography simulation and evaluation is performed on the design database utilizing a second set of performance indexes to verify the modification. If necessary, the design database is modified again based on a result of the second lithography simulation and evaluation. The modified design database is provided to a mask manufacturer for manufacturing the mask corresponding to the modified design database.

Abstract translation: 公开了一种执行OPC和评估OPC解决方案的方法。 一种示例性方法包括接收对应于IC电路掩码的设计数据库。 使用第一组性能指标对设计数据库执行第一光刻模拟和评估。 基于执行第一光刻仿真和评估的结果对设计数据库进行修改。 使用第二组性能指标对设计数据库执行第二次光刻模拟和评估，以验证修改。 如果需要，基于第二光刻模拟和评估的结果再次修改设计数据库。 将修改后的设计数据库提供给掩模制造商以制造与修改的设计数据库相对应的掩模。

公开(公告)号：US20140013287A1

公开(公告)日：2014-01-09

申请号：US13544014

申请日：2012-07-09

Applicant: Nian-Fuh Cheng ,  Yu-Po Tang ,  Chien-Fu Lee ,  Sheng-Wen Lin ,  Yong-Cheng Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

Inventor： Nian-Fuh Cheng ,  Yu-Po Tang ,  Chien-Fu Lee ,  Sheng-Wen Lin ,  Yong-Cheng Lin ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC: G06F17/50

CPC classification number: G03F7/70441 ,  G03F1/36 ,  G03F1/70

Abstract: The present disclosure describes an OPC method of preparing data for forming a mask. The method includes setting a plurality of dissection points at the main feature and further includes setting a target point at the main feature. The method includes arranging the two dissection points crossing the main feature symmetrically each other. The method includes separating two adjacent dissection points at one side of the main feature by a maximum resolution of the mask writer. The method includes dividing the main feature into a plurality of segments using the dissection points. The method includes performing an OPC convergence simulation to a target point. The method includes correcting the segments belonging to an ambit of the target point and further includes correcting the segment shared by two ambits.

Abstract translation: 本公开描述了制备用于形成掩模的数据的OPC方法。 该方法包括在主要特征处设置多个解剖点，并且还包括在主要特征处设置目标点。 该方法包括将两个解剖点布置成彼此对称的主要特征。 该方法包括通过掩模写入器的最大分辨率在主要特征的一侧分离两个相邻的解剖点。 该方法包括使用解剖点将主要特征划分成多个段。 该方法包括对目标点执行OPC收敛模拟。 该方法包括校正属于目标点的范围的段，并且还包括校正由两个方位共享的段。

公开(公告)号：US20130292841A1

公开(公告)日：2013-11-07

申请号：US13464055

申请日：2012-05-04

Applicant: Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

Inventor： Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

Abstract translation: 本公开提供了一种用于半导体器件的互连结构。 互连结构包括含有第一金属线的第一金属层。 互连结构包括位于第一金属层上方的电介质层。 电介质层包含电耦合到第一金属线的第一子通路和电耦合到第一子通路的第二子通路。 第二子通孔不同于第一子通孔。 互连结构包括位于电介质层上方的第二金属层。 第二金属层包含电耦合到第二子通孔的第二金属线。 第一金属层和第二金属层之间没有其他金属层。

公开(公告)号：US20130285246A1

公开(公告)日：2013-10-31

申请号：US13458396

申请日：2012-04-27

Applicant: Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

Inventor： Shih-Ming Chang ,  Ken-Hsien Hsieh ,  Tsong-Hua Ou ,  Ru-Gun Liu ,  Fang-Yu Fan ,  Yuan-Te Hou

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and method for fabricating a device is disclosed. An exemplary device includes a first conductive layer disposed over a substrate, the first conductive layer including a first plurality of conductive lines extending in a first direction. The device further includes a second conductive layer disposed over the first conductive layer, the second conductive layer including a second plurality of conductive lines extending in a second direction. The device further includes a self-aligned interconnect formed at an interface where a first conductive line of the first plurality of conductive lines is in electrical contact with a first conductive line of the second plurality of conductive lines. The device further includes a blocking portion interposed between a second conductive line of the first plurality of conductive lines and a second conductive line of the second plurality of conductive lines.

Abstract translation: 公开了一种用于制造装置的装置和方法。 示例性器件包括设置在衬底上的第一导电层，第一导电层包括沿第一方向延伸的第一多个导电线。 该装置还包括设置在第一导电层上的第二导电层，第二导电层包括沿第二方向延伸的第二多个导电线。 该装置还包括形成在第一多个导线的第一导线与第二多个导线的第一导线电接触的界面处的自对准互连。 该装置还包括插入在第一多个导线中的第二导线与第二多个导线之间的第二导线之间的阻挡部分。

公开(公告)号：US20130130410A1

公开(公告)日：2013-05-23

申请号：US13743087

申请日：2013-01-16

Applicant: Burn Jeng LIN ,  Tsai-Sheng GAU ,  Ru-Gun LIU ,  Wen-Chun HUANG

Inventor： Burn Jeng LIN ,  Tsai-Sheng GAU ,  Ru-Gun LIU ,  Wen-Chun HUANG

IPC: H01L21/66

CPC classification number: H01L22/10 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/31144 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask.

Abstract translation: 一种通过使用双重图案化技术对通孔层进行图案掩模分配的方法，所述方法包括使用处理器来确定通孔层的通孔是否拦截分配给第一金属掩模的下面或重叠的金属结构。 如果通孔截取分配给第一金属掩模的金属结构，则将通孔分配给第一通孔掩模，其中第一通孔掩模与第一金属掩模对准。 否则，将通孔分配给第二通孔掩模，其中第二通孔掩模与不同于第一金属掩模的第二金属掩模对准。

公开(公告)号：US08381153B2

公开(公告)日：2013-02-19

申请号：US12884442

申请日：2010-09-17

Applicant: Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J. H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

Inventor： Chia-Ping Chiang ,  Yu-Po Tang ,  Ming-Hui Chih ,  Cheng-Kun Tsai ,  Wei-Long Wang ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Tsai-Sheng Gau ,  Cheng-Lung Tsai ,  Josh J. H. Feng ,  Bing-Syun Yeh ,  Jeng-Shiun Ho ,  Cheng-Cheng Kuo

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes receiving an IC design layout having a plurality of main features; applying a main feature dissection to the main features of the IC design layout and generating sub-portions of the main features; performing an optical proximity correction (OPC) to the main features; performing a mask rule check (MRC) to a main feature of the IC design layout; and modifying one of the sub-portions of the main feature if the main feature fails the MRC.

Abstract translation: 本公开提供了集成电路（IC）设计方法的一个实施例。 该方法包括接收具有多个主要特征的IC设计布局; 将主要特征解剖应用于IC设计布局的主要特征，并生成主要特征的子部分; 对主要特征执行光学邻近校正（OPC）; 执行掩模规则检查（MRC）到IC设计布局的主要特征; 并且如果主要特征使MRC故障，则修改主要特征的一个子部分。

公开(公告)号：US08381139B2

公开(公告)日：2013-02-19

申请号：US13006608

申请日：2011-01-14

Applicant: Burn Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Wen-Chun Huang

Inventor： Burn Jeng Lin ,  Tsai-Sheng Gau ,  Ru-Gun Liu ,  Wen-Chun Huang

IPC: G06F17/50

CPC classification number: H01L22/10 ,  G03F1/70 ,  G03F7/70433 ,  G03F7/70466 ,  G06F17/5036 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/31144 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The embodiments of via mask splitting methods for double patterning technology described enable via patterning to align to a metal layer underneath or overlying to reduce overlay error and to increase via landing. If adjacent vias violate the G0-mask-split-rule for space or pitch (or both) between vias, the mask assignment of end vias are given higher priority to ensure good landing of end vias, since they are at higher risk of mislanding. The metal correlated via mask splitting methods enable better via performance, such as lower via resistance, and higher via yield.

Abstract translation: 所描述的用于双重图案化技术的通孔掩模分裂方法的实施例使得能够经由图案化以对准下面的金属层或覆盖以减少覆盖误差并增加通过着陆。 如果相邻的通孔违反了通孔之间的空间或间距（或两者）的G0-掩模分割规则，则优先考虑末端通孔的掩模分配，以确保最终通孔的良好着陆，因为它们具有较高的误放置风险。 通过掩模分离方法相关的金属能够实现更好的通过性能，例如较低的通孔电阻和较高的通孔产量。