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21.发明申请公开(公告)号：US20190213294A1
公开(公告)日：2019-07-11
申请号：US16207457
申请日：2018-12-03
Inventor： Dominik LUBELEY , Heiko KALTE
IPC: G06F17/50 , G06F16/901 , G06F16/903
Abstract: A method for generating an FPGA implementation based on an FPGA design serving as an FPGA model and/or a hardware description, including the steps of synthesizing a net list from the FPGA design and generating the FPGA implementation from the net list. The method includes searching for a similar FPGA implementation, the step of generating the FPGA implementation from the net list takes place using the similar FPGA implementation, the method includes a step of generating a graph-based representation based on the FPGA design, and the step of searching for a similar FPGA implementation comprises comparing the graph-based representation of the FPGA design with a graph-based representation of the at least one similar FPGA implementation. A method for generating a bit stream based on an FPGA design is also provided, serving as an FPGA model and/or a hardware description.
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公开(公告)号：US10338552B2
公开(公告)日：2019-07-02
申请号：US15433236
申请日：2017-02-15
Inventor： Joerg Bracker
Abstract: A simulation apparatus for simulating a peripheral circuit arrangement connected to a regulating device and has a first current controller for influencing a first load current and a second current controller for influencing a first source current. The first current controller is controlled by a model code and used to set the first load current, and the first load current is routed to a first load connection of the regulating device. The second current controller is controlled by the model code and used to set the first source current, which is routed to a first supply connection of the regulating device. The model code influences the model code on the first current controller and the second current controller allows the first load current to be recovered at least proportionally from the first source current and/or the first source current to be recovered at least proportionally from the first load current.
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公开(公告)号：US10331548B2
公开(公告)日：2019-06-25
申请号：US15229231
申请日：2016-08-05
Inventor： Frank Luenstroth , Renate Hein
Abstract: A computer-implemented method for testing a control program that is modeled as one or more blocks of a block diagram in a computing environment. A first user interface is provided for selecting a simulation mode for the block diagram and a second user interface is provided for selecting a compiler intended for production code compilation. When it is confirmed that a software-in-the-loop simulation mode has been selected in the first user interface, the blocks of the block diagram are converted to a production code and is compiled to an executable using the compiler selected in the second user interface. By running the executable on the host computer while recording one or more data points based on input/output signals and/or evaluating the compliance of the one or more data points to one or more criteria, the control program corresponding to the one or more blocks is tested.
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公开(公告)号：US10311193B2
公开(公告)日：2019-06-04
申请号：US14823197
申请日：2015-08-11
Inventor： Heiko Kalte , Lukas Funke
IPC: G06F17/50
Abstract: A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.
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25.发明申请公开(公告)号：US20190073437A1
公开(公告)日：2019-03-07
申请号：US16113560
申请日：2018-08-27
Inventor： Nicolas AMRINGER , Dominik HOLLER , Steffen BERINGER
IPC: G06F17/50
Abstract: A method for providing a real-time-capable simulation for control unit development, wherein the real-time-capable simulation simulates a control unit or an environment of a control unit or a combination of a control unit and an environment of the control unit. The real-time-capable simulation has a co-simulation of a real-time-capable sub-simulation and a non-real-time-capable sub-simulation that interacts with the real-time-capable sub-simulation, wherein the real-time-capable sub-simulation and the non-real-time-capable sub-simulation are designed for communication of simulation data. The real-time-capable sub-simulation has a first simulation time corresponding to real time and the non-real-time-capable sub-simulation has a virtual, second simulation time that is coupled to the first simulation time and that matches the first simulation time at the start of the real-time-capable simulation.
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Patent Agency Ranking
26.发明申请公开(公告)号：US20180349255A1
公开(公告)日：2018-12-06
申请号：US15996850
申请日：2018-06-04
Inventor： Matthias FROMME , Jochen SAUER , Matthias SCHMITZ
Abstract: A method and device for transmitting metrologically acquired and digitized measured data in a test device. The measured data corresponds to a program task, and a direction of the transmission of the measured data from a measured data transmitter of the test device is provided via a data channel to a measured data receiver of the test device. The measured data transmitter has a signal preprocessing processor, a task monitoring processor and a data channel arbiter. Via the task monitoring processor, a task ID data packet is generated at an execution start of the program task or at an execution end of the program task, and the task ID data packet is transmitted to the data channel arbiter. Via the data channel arbiter, the measured data and the task ID data packet are successively forwarded via the data channel as a data stream to the measuring data receiver.
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公开(公告)号：US20180088911A1
公开(公告)日：2018-03-29
申请号：US15273992
申请日：2016-09-23
Inventor： Sebastian MOORS , Michael MAIR , Tanja MOLDENHAUER , Volker STRAETGEN
IPC: G06F9/44
Abstract: A method for generating production code from a block diagram on a host computer is provided. A block in the block diagram has a number of input ports for receiving signals and a number of output ports for sending signals. The processor identifies a first block in the block diagram. The input signal is traced back to a second block upstream of the first block. Compliance with a optimization condition is checked, the optimization condition being fulfilled when a group of adjacent blocks has an assignment operation that affects one or more elements of the input signal while leaving at least one element of the composite variable unchanged. A combined production code is generated for the group of adjacent blocks when the optimization condition is fulfilled so that the combined production code includes write instructions for those elements of the composite variable that are affected by the assignment operation.
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公开(公告)号：US09928803B2
公开(公告)日：2018-03-27
申请号：US14640315
申请日：2015-03-06
Inventor： Sebastian Hillebrand , Karsten Fischer
IPC: G06F3/048 , G09G5/00 , G05B19/042 , G06F9/44
CPC classification number: G09G5/006 , G05B19/0426 , G05B2219/23217 , G05B2219/23258 , G05B2219/23266 , G05B2219/23292 , G06F8/34 , G09G2340/00
Abstract: A computer-implemented method for generating a control program that is executable on a control system from a graphical control model. A better utilization of the control system is achieved in that the graphical control model is translated into program code such that the generated program code has at least one FXP operation and at least one FLP operation, and in that the generated program code is translated into the executable control program such that when the control program is executed on the control system a portion of the control program is executed on the FXP unit and another portion of the control program is executed on the FLP unit.
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公开(公告)号：US09886294B2
公开(公告)日：2018-02-06
申请号：US14861071
申请日：2015-09-22
Inventor： Dominik Holler
IPC: G06F9/455 , G05B19/418
CPC classification number: G06F9/455 , G05B19/02 , G05B19/41885 , G06F9/45504 , G06F9/45533 , G06F9/45558 , G06F2009/45583 , Y02P90/26
Abstract: A method for executing a first application program of a first control unit on a computer, wherein functions for controlling actuators and/or sensors and/or functions for processing and/or providing data from actuators and/or sensors are executed by the first application program. A first interface between a control unit hardware and a first application program of the control unit is established by the control unit operating system. A first virtual control unit operating system and a first virtual application program are generated by compilation. A simulation environment interface is made available by the simulation environment for transfer of a data item and/or of an event to the first virtual application program and/or the virtual control unit operating system. The simulation environment initiates and controls an execution of the first virtual application program within the control unit operating system within the first virtual machine through the simulation environment interface.
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公开(公告)号：US20170329877A1
公开(公告)日：2017-11-16
申请号：US15585335
申请日：2017-05-03
Inventor： Heiko KALTE , Dominik LUBELEY
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F17/5027 , G06F17/5054
Abstract: A method for creating an FPGA netlist generated from an FPGA source code and at least one shadow register. The FPGA source code defines at least one function and at least one signal. The shadow register is assigned to the at least one signal, and is arranged and provided to store the value of the assigned signal at runtime. An option for reading out the stored signal value at runtime is provided. The function defined in the FPGA source code is not changed by the shadow register. The function described by the FPGA source code is executed by the FPGA, and a functional decoupling of the shadow register from the function described in the FPGA source code is provided. Via the decoupling, the shadow register maintains the signal value stored at the time of the decoupling while the function described in the FPGA source code is being executed.
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