公开(公告)号：US09239804B2

公开(公告)日：2016-01-19

申请号：US14045701

申请日：2013-10-03

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Andrew Kegel ,  Jimshed Mirza ,  Paul Blinzer ,  Philip Ng

IPC: G06F11/07 ,  G06F13/00 ,  G06F12/10 ,  G06F12/00 ,  G06F13/38

CPC classification number: G06F13/00 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0793 ,  G06F12/00 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F13/385 ,  Y02D10/14 ,  Y02D10/151

Abstract: A system and method of managing requests from peripherals in a computer system are provided. In the system and method, an input/output memory management unit (IOMMU) receives a peripheral page request (PPR) from a peripheral. In response to a determination that a criterion regarding an available capacity of a PPR log is satisfied, a completion message is sent to the peripheral indicating that the PPR is complete and the PPR is discarded without queuing the PPR in the PPR log.

Abstract translation: 提供了一种在计算机系统中管理来自外围设备的请求的系统和方法。 在系统和方法中，输入/输出存储器管理单元（IOMMU）从外设接收外围寻呼请求（PPR）。 响应于满足关于PPR日志的可用容量的标准的确定，向外设发送完成消息，指示PPR完成并且PPR被丢弃，而不在PPR日志中排队PPR。

公开(公告)号：US12105634B2

公开(公告)日：2024-10-01

申请号：US17486131

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang ,  Jimshed Mirza

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/68

Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.

公开(公告)号：US10580110B2

公开(公告)日：2020-03-03

申请号：US15496637

申请日：2017-04-25

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Al Hasanur Rahman ,  Sergey Korobkov ,  Houman Namiranian

IPC: G06T1/60 ,  G06F13/24 ,  G06F12/1009 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

公开(公告)号：US20230103230A1

公开(公告)日：2023-03-30

申请号：US17486131

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang ,  Jimshed Mirza

IPC: G06F12/1027

Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.

公开(公告)号：US10545887B2

公开(公告)日：2020-01-28

申请号：US15442402

申请日：2017-02-24

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Qian Ma

IPC: G06F13/16

Abstract: A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue for a single requestor. The buffer maintains multiple head pointers and multiple tail pointers for the single requestor. Data entries of the single logical queue are stored in an alternating pattern among the multiple linked lists. During the allocation of buffer entries, the tail pointers are selected in the same alternating manner, and during the deallocation of buffer entries, the multiple head pointers are selected in the same manner.

公开(公告)号：US20180308216A1

公开(公告)日：2018-10-25

申请号：US15496637

申请日：2017-04-25

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Al Hasanur Rahman ,  Sergey Korobkov ,  Houman Namiranian

IPC: G06T1/60 ,  G06T1/20 ,  G06F13/24 ,  G06F12/1009 ,  G06F12/121

CPC classification number: G06T1/60 ,  G06F12/1009 ,  G06F12/121 ,  G06F13/24

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

公开(公告)号：US20180246820A1

公开(公告)日：2018-08-30

申请号：US15442402

申请日：2017-02-24

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Qian Ma

IPC: G06F13/16

Abstract: A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue for a single requestor. The buffer maintains multiple head pointers and multiple tail pointers for the single requestor. Data entries of the single logical queue are stored in an alternating pattern among the multiple linked lists. During the allocation of buffer entries, the tail pointers are selected in the same alternating manner, and during the deallocation of buffer entries, the multiple head pointers are selected in the same manner.

公开(公告)号：US20180232316A1

公开(公告)日：2018-08-16

申请号：US15433560

申请日：2017-02-15

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Anthony Chan ,  Edwin Chi Yeung Pang

IPC: G06F12/1027 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/1009 ,  G06F2212/657 ,  G06F2212/68

Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.

公开(公告)号：US10241925B2

公开(公告)日：2019-03-26

申请号：US15433560

申请日：2017-02-15

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Anthony Chan ,  Edwin Chi Yeung Pang

IPC: G06F12/10 ,  G06F12/1027 ,  G06F12/1009

Abstract: Systems, apparatuses, and methods for selecting default page sizes in a variable page size translation lookaside buffer (TLB) are disclosed. In one embodiment, a system includes at least one processor, a memory subsystem, and a first TLB. The first TLB is configured to allocate a first entry for a first request responsive to detecting a miss for the first request in the first TLB. Prior to determining a page size targeted by the first request, the first TLB specifies, in the first entry, that the first request targets a page of a first page size. Responsive to determining that the first request actually targets a second page size, the first TLB reissues the first request with an indication that the first request targets the second page size. On the reissue, the first TLB allocates a second entry and specifies the second page size for the first request.