公开(公告)号：US12169876B2

公开(公告)日：2024-12-17

申请号：US17564138

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Anthony H C Chan ,  Christopher J. Brennan ,  Mark Fowler ,  David Chui ,  Leon K. N. Lai ,  Jimshed Mirza

IPC: G06T1/20 ,  G06T7/10 ,  G06T7/90 ,  G06T15/00 ,  H04N1/60 ,  H04N19/13 ,  H04N19/59

Abstract: A processor for optimizing partial writes to compressed blocks is configured to identify that a write request targets less than an entirety of a compressed block of pixel data, identify, based on a compression key, a compressed segment of the compressed block of pixel data that includes a target of the write request, and decompress, responsive to the write request, only the identified compressed segment of the compressed block of pixel data.

公开(公告)号：US20200019530A1

公开(公告)日：2020-01-16

申请号：US16042592

申请日：2018-07-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Yunpeng Zhu ,  Jimshed Mirza

IPC: G06F15/80

Abstract: A method and system for partial wavefront merger is described. Vector processing machines employ the partial wavefront merger to merge partial wavefronts into one or more wavefronts. The system includes a partial wavefront manager and unified registers. The partial wavefront manager detects wavefronts in different single-instruction-multiple-data (“SIMD”) units which contain inactive work items and active work items (hereinafter referred to as “partial wavefronts”), moves the partial wavefronts into one or more SIMD unit(s) and merges the partial wavefronts into one or more wavefront(s). The unified register allows each active work item in the one or more merged wavefront(s) to access the previously allocated registers in the originating SIMD units. Consequently, the contents of the unified registers do not have to be copied to the SIMD unit(s) executing the one or merged wavefront(s).

公开(公告)号：US20180181488A1

公开(公告)日：2018-06-28

申请号：US15390080

申请日：2016-12-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Mark Fowler ,  Jimshed Mirza ,  Anthony Asaro

IPC: G06F12/0804 ,  G06F12/0891 ,  G06F12/1009 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques for performing cache invalidates and write-backs in an accelerated processing device (e.g., a graphics processing device that renders three-dimensional graphics) are disclosed. The techniques involve receiving requests from a “master” (e.g., the central processing unit). The techniques involve invalidating virtual-to-physical address translations in an address translation request. The techniques include splitting up the requests based on whether the requests target virtually or physically tagged caches. Addresses for the portions of a request that target physically tagged caches are translated using invalidated virtual-to-physical address translations for speed. The split up request is processed to generate micro-transactions for individual caches targeted by the request. Micro-transactions for physically and virtually tagged caches are processed in parallel. Once all micro-transactions for a request have been processed, the unit that made the request is notified.

公开(公告)号：US12105634B2

公开(公告)日：2024-10-01

申请号：US17486131

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang ,  Jimshed Mirza

IPC: G06F12/10 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F2212/68

Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.

公开(公告)号：US20230206559A1

公开(公告)日：2023-06-29

申请号：US17562653

申请日：2021-12-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Christopher J. Brennan ,  Randy Wayne Ramsey ,  Nishank Pathak ,  Ricky Wai Yeung Iu ,  Jimshed Mirza ,  Anthony Chan

IPC: G06T17/20 ,  G06T17/10 ,  G06T15/00 ,  G06T1/60

CPC classification number: G06T17/20 ,  G06T17/10 ,  G06T15/005 ,  G06T1/60

Abstract: Systems, apparatuses, and methods for implementing a discard engine in a graphics pipeline are disclosed. A system includes a graphics pipeline with a geometry engine launching shaders that generate attribute data for vertices of each primitive of a set of primitives. The attribute data is consumed by pixel shaders, with each pixel shader generating a deallocation message when the pixel shader no longer needs the attribute data. A discard engine gathers deallocations from multiple pixel shaders and determines when the attribute data is no longer needed. Once a block of attributes has been consumed by all potential pixel shader consumers, the discard engine deallocates the given block of attributes. The discard engine sends a discard command to the caches so that the attribute data can be invalidated and not written back to memory.

公开(公告)号：US10580110B2

公开(公告)日：2020-03-03

申请号：US15496637

申请日：2017-04-25

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Al Hasanur Rahman ,  Sergey Korobkov ,  Houman Namiranian

IPC: G06T1/60 ,  G06F13/24 ,  G06F12/1009 ,  G06F12/121

Abstract: Systems, apparatuses, and methods for tracking page reuse and migrating pages are disclosed. In one embodiment, a system includes one or more processors, a memory access monitor, and multiple memory regions. The memory access monitor tracks accesses to memory pages in a system memory during a programmable interval. If the number of accesses to a given page is greater than a programmable threshold during the programmable interval, then the memory access monitor generates an interrupt for software to migrate the given page from the system memory to a local memory. If the number of accesses to the given page is less than or equal to the programmable threshold during the programmable interval, then the given page remains in the system memory. After the programmable interval, the memory access monitor starts tracking the number of accesses to a new page in a subsequent interval.

公开(公告)号：US10535178B2

公开(公告)日：2020-01-14

申请号：US15389075

申请日：2016-12-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Jimshed Mirza ,  Christopher J. Brennan ,  Anthony Chan ,  Leon Lai

IPC: G06T15/50 ,  G06T15/00 ,  G06F12/0875 ,  G06T15/04 ,  G06T15/80

Abstract: Systems, apparatuses, and methods for performing shader writes to compressed surfaces are disclosed. In one embodiment, a processor includes at least a memory and one or more shader units. In one embodiment, a shader unit of the processor is configured to receive a write request targeted to a compressed surface. The shader unit is configured to identify a first block of the compressed surface targeted by the write request. Responsive to determining the data of the write request targets less than the entirety of the first block, the first shader unit reads the first block from the cache and decompress the first block. Next, the first shader unit merges the data of the write request with the decompressed first block. Then, the shader unit compresses the merged data and writes the merged data to the cache.

公开(公告)号：US20230103230A1

公开(公告)日：2023-03-30

申请号：US17486131

申请日：2021-09-27

Applicant: ATI TECHNOLOGIES ULC

Inventor： Edwin Pang ,  Jimshed Mirza

IPC: G06F12/1027

Abstract: A processing system includes a translation lookaside buffer (TLB). The TLB includes a plurality of TLB entries that are configured to store requested page size indications. The TLB is configured to be indexed via the requested page size indications such that a plurality of TLB requests that each indicate a same virtual address, but different respective requested page sizes are allocated respective TLB entries. As a result, in response to a TLB request that indicates a requested page size and has a virtual address that corresponds to multiple TLB entries, only a single TLB entry is identified as a TLB hit.

公开(公告)号：US10606740B2

公开(公告)日：2020-03-31

申请号：US15607118

申请日：2017-05-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Yunpeng Zhu ,  Jimshed Mirza

IPC: G06F12/02 ,  G06F9/38 ,  G06F9/48 ,  G06T1/60 ,  G06T15/00 ,  G06F12/0811 ,  G06F9/30 ,  G06F12/084

Abstract: Systems, apparatuses, and methods for generating flexibly addressed memory requests are disclosed. In one embodiment, a system includes a processor, control unit, and memory subsystem. The processor launches a plurality of threads on a plurality of compute units, wherein each thread generates memory requests without specifying target memory addresses. The threads executing on the plurality of compute units convey a plurality of memory requests to the control unit. The control unit generates target memory addresses for the plurality of received memory requests. In one embodiment, the memory requests are write requests, and the control unit interleaves write requests from the plurality of threads into a single output buffer stored in the memory subsystem. The control unit can be located in a cache, in a memory controller, or in another location within the system.

公开(公告)号：US10545887B2

公开(公告)日：2020-01-28

申请号：US15442402

申请日：2017-02-24

Applicant: ATI Technologies ULC

Inventor： Jimshed Mirza ,  Qian Ma

IPC: G06F13/16

Abstract: A system and method for maintaining information of pending operations are described. A buffer uses multiple linked lists implementing a single logical queue for a single requestor. The buffer maintains multiple head pointers and multiple tail pointers for the single requestor. Data entries of the single logical queue are stored in an alternating pattern among the multiple linked lists. During the allocation of buffer entries, the tail pointers are selected in the same alternating manner, and during the deallocation of buffer entries, the multiple head pointers are selected in the same manner.