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公开(公告)号：US11132010B1
公开(公告)日：2021-09-28
申请号：US16905031
申请日：2020-06-18
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia
IPC: H03K5/153 , G05F1/46 , G01R21/133 , G04F10/00
Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.
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公开(公告)号：US10903824B2
公开(公告)日：2021-01-26
申请号：US16804675
申请日：2020-02-28
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Wenhao Li
IPC: H03K3/037 , H03K19/0185
Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.
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公开(公告)号：US20200373915A1
公开(公告)日：2020-11-26
申请号：US16989621
申请日：2020-08-10
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US10191086B2
公开(公告)日：2019-01-29
申请号：US15079364
申请日：2016-03-24
Applicant: Apple Inc.
Inventor： Michael R. Seningen , Zhao Wang , Ajay Bhatia
Abstract: An apparatus for detecting a change in a voltage level of a power supply is disclosed. An inverter coupled to a first power supply may generate a signal dependent upon a voltage level of a second power supply. A latch coupled to the first power supply may be set based on a first voltage level of the second power supply and a first value of the signal, and re-set based on a second voltage level of the second power supply and a second value of the signal different than the first value of the signal.
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公开(公告)号：US09411392B2
公开(公告)日：2016-08-09
申请号：US14295997
申请日：2014-06-04
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Michael Dreesen
CPC classification number: G06F1/3203 , G06F12/0223 , G06F12/06 , G06F2212/1016 , G11C5/14 , G11C5/147 , G11C7/1096 , G11C11/419
Abstract: A system for storing data in a memory may include circuitry that may receive an address, a command and data. The circuitry may also determine a type of the command and generate a read control or write control signal dependent upon the type. The system may also include a plurality of sub-arrays and sense amplifiers. Each of the sub-arrays may include a plurality of memory cells. Each of the sense amplifiers may be coupled to a respective one of the plurality of sub-arrays and may read data stored in a first memory cell included in the respective sub-array. The system may also include one or more write driver circuits. A first write driver circuit may be coupled to at least two of the plurality of sub-arrays. The first write driver circuit may be configured to store data into a second memory cell in one of the at least two sub-arrays.
Abstract translation: 用于将数据存储在存储器中的系统可以包括可以接收地址，命令和数据的电路。 电路还可以确定命令的类型，并根据该类型生成读控制或写控制信号。 该系统还可以包括多个子阵列和感测放大器。 每个子阵列可以包括多个存储单元。 每个读出放大器可以耦合到多个子阵列中的相应一个子阵列，并且可以读取存储在包括在相应子阵列中的第一存储单元中的数据。 该系统还可以包括一个或多个写入驱动器电路。 第一写入驱动器电路可以耦合到多个子阵列中的至少两个。 第一写入驱动器电路可以被配置为将数据存储在至少两个子阵列之一中的第二存储器单元中。
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Patent Agency Ranking
公开(公告)号：US09189052B2
公开(公告)日：2015-11-17
申请号：US14296066
申请日：2014-06-04
Applicant: Apple Inc.
Inventor： Ajay Bhatia , Michael Dreesen
CPC classification number: G06F1/3203 , G06F12/0223 , G06F12/06 , G06F2212/1016 , G11C5/14 , G11C5/147 , G11C7/1096 , G11C11/419
Abstract: A system, a voltage regulator and a method for regulating power are disclosed, wherein the system may include a processor, a voltage regulator circuit, and a memory unit. The voltage regulator circuit may be configured to generate a first power supply voltage provided to the memory unit. The voltage regulator circuit may be further configured to adjust a voltage level of two output nodes dependent upon a level of the first power supply voltage and a level of a reference voltage. The voltage regulator circuit may be further configured to adjust the level of the first power supply signal dependent upon the level of at least one of the two output voltages. The voltage regulating circuit may also provide the first output voltage to the second output voltage via an impedance.
Abstract translation: 公开了一种系统，电压调节器和用于调节功率的方法，其中系统可以包括处理器，电压调节器电路和存储器单元。 电压调节器电路可以被配置为产生提供给存储器单元的第一电源电压。 电压调节器电路还可以被配置为根据第一电源电压的电平和参考电压的电平来调整两个输出节点的电压电平。 电压调节器电路还可以被配置为根据两个输出电压中的至少一个的电平来调节第一电源信号的电平。 电压调节电路还可以经由阻抗将第一输出电压提供给第二输出电压。
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公开(公告)号：US20140112429A1
公开(公告)日：2014-04-24
申请号：US13658115
申请日：2012-10-23
Applicant: APPLE INC.
Inventor： Ajay Bhatia , Greg M. Hess , Sanjay P. Zambare
IPC: G11C19/28
CPC classification number: G11C19/28 , G11C11/412 , G11C2207/007
Abstract: A register file cell structure to enable lower voltage writes is disclosed. In one embodiment, a register file includes a state element made up of two cross-coupled inverters. Each of the inverters includes a p-channel metal oxide semiconductor (PMOS) transistor having a source terminal coupled to a virtual voltage node. One or more PMOS transistors are coupled in series between the virtual voltage node and a global voltage node. Each of the one or more PMOS transistors includes a gate terminal that is hardwired to a ground node, and thus these devices remain active when power is applied to the global voltage node. The presence of the one or more PMOS devices coupled between the virtual and global voltage nodes results in the ability to overwrite contents stored in the state element at lower voltages than otherwise attainable without the one or more PMOS devices.
Abstract translation: 公开了一种用于实现较低电压写入的寄存器文件单元结构。 在一个实施例中，寄存器文件包括由两个交叉耦合的反相器组成的状态元件。 每个反相器包括具有耦合到虚拟电压节点的源极端子的p沟道金属氧化物半导体（PMOS）晶体管。 一个或多个PMOS晶体管串联耦合在虚拟电压节点和全局电压节点之间。 一个或多个PMOS晶体管中的每一个包括硬接线到接地节点的栅极端子，因此当向全局电压节点施加功率时，这些器件保持有效。 耦合在虚拟和全局电压节点之间的一个或多个PMOS器件的存在导致在没有一个或多个PMOS器件的情况下以比其它可获得的电压更低的电压来覆盖存储在状态元件中的内容的能力。
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公开(公告)号：US11870442B2
公开(公告)日：2024-01-09
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
CPC classification number: H03K3/0372 , G06F1/08 , G06F1/28
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US20220345117A1
公开(公告)日：2022-10-27
申请号：US17812089
申请日：2022-07-12
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Raghava Rao V. Denduluri , Ajay Bhatia , Suparn Vats , Suresh Balasubramanian , Gopinath Venkatesh , Teng Wang
Abstract: An apparatus includes a control circuit configured to selectively activate, based on an operating mode signal, either a local clock signal or a pulse signal. The apparatus further includes a data storage circuit that is coupled to a data signal, the local clock signal, and the pulse signal. The data storage circuit may be configured to sample the data signal using the local clock signal during a first operating mode, and to sample the data signal using the pulse signal during a second operating mode.
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公开(公告)号：US11424734B2
公开(公告)日：2022-08-23
申请号：US17327365
申请日：2021-05-21
Applicant: Apple Inc.
Inventor： Vivekanandan Venugopal , Ajay Bhatia , Qi Ye
Abstract: Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.
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