公开(公告)号：US20190132797A1

公开(公告)日：2019-05-02

申请号：US16140317

申请日：2018-09-24

Applicant: APPLE INC.

Inventor： Richard M. Solotke ,  Saurabh Garg ,  Haining Zhang

IPC: H04W52/02

Abstract: Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive “wake” requests from the peripheral processor.

公开(公告)号：US20190042336A1

公开(公告)日：2019-02-07

申请号：US15840473

申请日：2017-12-13

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F9/54 ,  G06F13/362

Abstract: Methods and apparatus for scheduling time sensitive operations among independent processors. In one embodiment, an application processor (AP) determines transmission timing parameters for a baseband processor (BB). Thereafter, the AP can generate and transact generic time-sensitive RTP data with the BB in time for transmission via a Long Term Evolution (LTE) communication stack. In this manner, the AP's scheduler can coordinate/accommodate digital audio tasks within the context of its other tasks (e.g., to enable intelligent sleep and wake-up operation, load balancing, memory usage, and/or any number of other processor management functions).

公开(公告)号：US10198364B2

公开(公告)日：2019-02-05

申请号：US15271102

申请日：2016-09-20

Applicant: Apple Inc.

Inventor： Saurabh Garg ,  Karan Sanghi ,  Vladislav Petkov ,  Haining Zhang

IPC: G06F12/00 ,  G06F12/14 ,  G06F12/1081

Abstract: Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

公开(公告)号：US09830289B2

公开(公告)日：2017-11-28

申请号：US14856283

申请日：2015-09-16

Applicant: Apple Inc.

Inventor： Radha Kumar Pulyala ,  Saurabh Garg ,  Karan Sanghi

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/287 ,  G06F13/4022 ,  G06F13/4282

Abstract: Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wireless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface.

公开(公告)号：US20170215145A1

公开(公告)日：2017-07-27

申请号：US15008229

申请日：2016-01-27

Applicant: APPLE INC.

Inventor： Richard M. Solotke ,  Saurabh Garg ,  Haining Zhang

IPC: H04W52/02

CPC classification number: H04W52/0235 ,  Y02D70/1262 ,  Y02D70/1264 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/166

Abstract: Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive “wake” requests from the peripheral processor.

公开(公告)号：US11347567B2

公开(公告)日：2022-05-31

申请号：US16933826

申请日：2020-07-20

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg

IPC: G06F9/44 ,  G06F9/54 ,  G06F15/173 ,  G06F9/38

Abstract: Methods and apparatus for transacting multiple data flows between multiple processors. In one such implementation, multiple data pipes are aggregated over a common transfer data structure. Completion status information corresponding to each data pipe is provided over individual completion data structures. Allocating a common fixed pool of resources for data transfer can be used in a variety of different load balancing and/or prioritization schemes; however, individualized completion status allows for individualized data pipe reclamation. Unlike prior art solutions which dynamically created and pre-allocated memory space for each data pipe individually, the disclosed embodiments can only request resources from a fixed pool. In other words, outstanding requests are queued (rather than immediately serviced with a new memory allocation), thus overall bandwidth remains constrained regardless of the number of data pipes that are opened and/or closed.

公开(公告)号：US11068326B2

公开(公告)日：2021-07-20

申请号：US16505446

申请日：2019-07-08

Applicant: Apple Inc.

Inventor： Jason McElrath ,  Karan Sanghi ,  Saurabh Garg

IPC: G06F13/42 ,  G06F9/54 ,  G06F13/362 ,  H04L25/00 ,  G06F9/46 ,  G06F13/16 ,  H04W84/04 ,  H04W72/12

Abstract: Methods and apparatus for time sensitive data transfer between logical domains. In one embodiment, an user equipment (UE) device has an application processor (AP) coupled to a baseband processor (BB) that operate independently of one another normally, but may cooperate in limited hybrid use scenarios. For example, the BB receives audio packets via a cellular network that are converted to pulse code modulated (PCM) digital audio to be played by the AP. Unfortunately, since the AP and the BB are independently clocked, they will experience some clock drift. As a result, the audio playback may have undesirable artifacts if the drift is not otherwise compensated for. To these ends, the AP and/or BB determine a relative clock drift and compensate for playback by e.g., adding, padding, or deleting audio samples and/or audio packets. Techniques for handover scenarios are also disclosed.

公开(公告)号：US10789198B2

公开(公告)日：2020-09-29

申请号：US16450767

申请日：2019-06-24

Applicant: Apple Inc.

Inventor： Vladislav Petkov ,  Saurabh Garg ,  Karan Sanghi ,  Haining Zhang

IPC: G06F15/17 ,  G06F13/42 ,  H04W4/80

Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

公开(公告)号：US10684670B2

公开(公告)日：2020-06-16

申请号：US16390998

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Karan Sanghi ,  Saurabh Garg ,  Haining Zhang

IPC: G06F9/00 ,  G06F1/3293 ,  G06F1/3287 ,  G06F13/42 ,  G06F9/4401 ,  G06F1/3228 ,  G06F1/3234 ,  G06F11/14

Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

公开(公告)号：US20200104195A1

公开(公告)日：2020-04-02

申请号：US16179667

申请日：2018-11-02

Applicant: Apple Inc.

Inventor： KARAN SANGHI ,  Saurabh Garg

IPC: G06F9/54 ,  G06F9/46

Abstract: Methods and apparatus for correcting out-of-order data transactions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, a peripheral-side processor receives data from an external device and stores it to memory. The host processor writes data structures (transfer descriptors) describing the received data, regardless of the order the data was received from the external device. The transfer descriptors are written to a memory structure (transfer descriptor ring) in memory shared between the host and peripheral processors. The peripheral reads the transfer descriptors and writes data structures (completion descriptors) to another memory structure (completion descriptor ring). The completion descriptors are written to enable the host processor to retrieve the stored data in the correct order. In optimized variants, a completion descriptor describes groups of transfer descriptors. In some variants, the peripheral processor caches the transfer descriptors to offload them from the transfer descriptor ring.