-
公开(公告)号：US10558580B2
公开(公告)日：2020-02-11
申请号：US15273398
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
-
2.发明申请公开(公告)号：US20190034368A1
公开(公告)日：2019-01-31
申请号：US16056374
申请日：2018-08-06
Applicant: Apple Inc.
Inventor： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
CPC classification number: G06F13/28 , G06F13/4027 , Y02D10/14 , Y02D10/151
Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
-
公开(公告)号：US20180088660A1
公开(公告)日：2018-03-29
申请号：US15721200
申请日：2017-09-29
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
CPC classification number: G06F1/3293 , G06F1/3228 , G06F1/3243 , G06F1/3287 , G06F9/4403 , G06F9/4405 , G06F9/4411 , G06F11/1417 , G06F11/1471 , G06F11/1474 , G06F13/4282 , G06F2201/805 , G06F2201/87 , Y02D10/122 , Y02D10/14 , Y02D10/151 , Y02D10/152 , Y02D10/171
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
-
公开(公告)号：US20170249164A1
公开(公告)日：2017-08-31
申请号：US15273413
申请日：2016-09-22
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Haining Zhang , Karan Sanghi , Saurabh Garg
IPC: G06F9/44 , G06F12/1009 , G06F12/14 , G06F13/42
Abstract: Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.
-
5.发明申请METHODS AND APPARATUS FOR CONTROLLED RECOVERY OF ERROR INFORMATION BETWEEN INDEPENDENTLY OPERABLE PROCESSORS 有权控制恢复独立运行处理器之间的错误信息的方法和装置公开(公告)号：US20160224442A1
公开(公告)日：2016-08-04
申请号：US14870923
申请日：2015-09-30
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Vladislav Petkov , Haining Zhang
CPC classification number: G06F11/2028 , G06F13/4022 , G06F13/4221 , G06F2201/805
Abstract: Methods and apparatus for controlled recovery of error information between two (or more) independently operable processors. The present disclosure provides solutions that preserve error information in the event of a fatal error, coordinate reset conditions between independently operable processors, and implement consistent frameworks for error information recovery across a range of potential fatal errors. In one exemplary embodiment, an applications processor (AP) and baseband processor (BB) implement an abort handler and power down handler sequence which enables error recovery over a wide range of crash scenarios. In one variant, assertion of signals between the AP and the BB enables the AP to reset the BB only after error recovery procedures have successfully completed.
Abstract translation: 用于在两个（或多个）可独立操作的处理器之间控制恢复错误信息的方法和装置。 本公开提供了在致命错误的情况下保留错误信息，在独立可操作的处理器之间协调复位条件并且实现用于在一系列潜在致命错误中进行错误信息恢复的一致框架的解决方案。 在一个示例性实施例中，应用处理器（AP）和基带处理器（BB）实现中止处理器和掉电处理程序序列，其能够在广泛的崩溃情况下进行错误恢复。 在一种变型中，AP和BB之间的信号断言使AP能够在错误恢复过程成功完成后重置BB。
-
Patent Agency Ranking
公开(公告)号：US11176068B2
公开(公告)日：2021-11-16
申请号：US16780743
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
-
7.发明申请公开(公告)号：US20200249744A1
公开(公告)日：2020-08-06
申请号：US16780734
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
IPC: G06F1/3293 , G06F11/14 , G06F9/4401 , G06F1/3234 , G06F1/3228 , G06F13/42 , G06F1/3287
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
-
8.发明申请公开(公告)号：US20200174953A1
公开(公告)日：2020-06-04
申请号：US16780743
申请日：2020-02-03
Applicant: Apple Inc.
Inventor： Karan Sanghi , Vladislav Petkov , Radha Kumar Pulyala , Saurabh Garg , Haining Zhang
Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.
-
公开(公告)号：US10331612B1
公开(公告)日：2019-06-25
申请号：US15865638
申请日：2018-01-09
Applicant: Apple Inc.
Inventor： Vladislav Petkov , Saurabh Garg , Karan Sanghi , Haining Zhang
CPC classification number: G06F15/17 , G06F13/4221 , H04W4/80
Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.
-
10.发明申请公开(公告)号：US20190086993A1
公开(公告)日：2019-03-21
申请号：US16133543
申请日：2018-09-17
Applicant: Apple Inc.
Inventor： Karan Sanghi , Saurabh Garg , Haining Zhang
Abstract: Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.
-
-
-
-
-
-
-
-
-
Search Results
48
records
(took 0.026 seconds)
