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公开(公告)号：US09472158B2
公开(公告)日：2016-10-18
申请号：US14660355
申请日：2015-03-17
Applicant: APPLE INC.
Inventor： Hung Sheng Lin , Chaohao Wang , Szu-Hsien Lee , Weijun Yao , Yingxuan Li , Wonjae Choi
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3648 , G09G3/3688 , G09G2310/027 , G09G2310/0289 , G09G2310/0291 , G09G2320/0209 , G09G2320/029 , G09G2330/06 , G09G2330/08
Abstract: Systems and methods are provided for adjusting and displaying image data to account for variable common voltage error across separate common electrode sub-plates. The image data may be adjusted based on a common mode common voltage error on a common voltage line coupled to more than one different common electrode sub-plate. Each common electrode sub-plate may carry a common voltage that varies depending on values of the image data programmed to pixels associated with that common electrode sub-plate.
Abstract translation: 提供了系统和方法来调整和显示图像数据，以解决跨单独的公共电极子板的可变共同电压误差。 可以基于耦合到多于一个不同公共电极子板的公共电压线上的共模公共电压误差来调整图像数据。 每个公共电极子板可以承载根据编程到与该公共电极子板相关联的像素的图像数据的值而变化的公共电压。
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公开(公告)号：US20160098144A1
公开(公告)日：2016-04-07
申请号：US14923246
申请日：2015-10-26
Applicant: Apple Inc.
Inventor： Byung Duk Yang , Szu-Hsien Lee , Kyung Wook Kim , Shih Chang Chang , Chun-Yao Huang , Hao-Lin Chiu
CPC classification number: G09G3/3648 , G02F1/13338 , G02F1/134309 , G02F1/1345 , G02F1/136286 , G02F1/1368 , G02F2001/13456 , G06F3/0412 , G06F3/0416 , G06F3/044 , G06F2203/04103 , G06F2203/04104 , G06F2203/04112 , G09F9/30 , G09G3/3666 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0426 , G09G2310/0281 , H01L23/5226 , H01L23/528 , H01L27/124 , H01L2924/0002 , H01L2924/00
Abstract: A display may have an array of pixels arranged in rows and columns. Each pixel may have a transistor for controlling the amount of output light associated with that pixel. The transistors may be thin-film transistors having active areas, first and second source-drain terminals, and gates. Gate lines may be used to distribute gate control signals to the gates of the transistors in each row. Data lines that run perpendicular to the gate lines may be used to distribute image data along columns of pixels. The gate lines may be connected to gate line extensions that run parallel to the data lines. The data lines may each overlap a respective one of the gate line extensions. Vias may be used to connect the gate line extensions to the gate lines. The gate line extensions may all have the same length.
Abstract translation: 显示器可以具有排列成行和列的像素阵列。 每个像素可以具有用于控制与该像素相关联的输出光量的晶体管。 晶体管可以是具有有源区的薄膜晶体管，第一和第二源极 - 漏极端子和栅极。 栅极线可用于将栅极控制信号分配到每行中的晶体管的栅极。 垂直于栅极线延伸的数据线可用于沿像素列分布图像数据。 栅极线可以连接到平行于数据线延伸的栅极线扩展。 数据线可以各自重叠相应的一个栅极线延伸。 通孔可用于将栅极线延伸部分连接到栅极线。 门线扩展可能都具有相同的长度。
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23.发明申请公开(公告)号：US20160042707A1
公开(公告)日：2016-02-11
申请号：US14472272
申请日：2014-08-28
Applicant: Apple Inc.
Inventor： Chaohao WANG , Szu-Hsien Lee , Paolo SACCHETTO , Shih Chang Chang , Chun-Yao Huang , Paul S. DRZAIC
CPC classification number: G09G3/3266 , G09G3/2044 , G09G3/3225 , G09G3/3648 , G09G2310/04 , G09G2320/0247 , G09G2320/0673 , G09G2330/021 , G09G2340/0435
Abstract: This application relates to methods and apparatus for refreshing a display device at various frequencies. Specifically, multiple areas of the display device can be refreshed concurrently at different frequencies. In this way, when static content is being displayed in certain areas of the display device, those certain areas can be refreshed at a lower rate than areas displaying dynamic content such as video or animation. By refreshing at lower rates, the energy consumed by the display device and subsystems associated with the display device can be reduced. Additionally, processes for reducing flicker when refreshing the display device at different refresh rates are disclosed herein.
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公开(公告)号：US20150220194A1
公开(公告)日：2015-08-06
申请号：US14489338
申请日：2014-09-17
Applicant: Apple Inc.
Inventor： Chin-Wei Lin , Chun-Yao Huang , Shih Chang Chang , Szu-Hsien Lee
IPC: G06F3/041
CPC classification number: G06F3/0412 , G06F3/0416
Abstract: A touch screen display may include gate line driver circuitry coupled to a display pixel array. The display may be provided with intra-frame pausing, (IFP) capabilities, where touch or other operations may be performed during one or more intra-frame blanking intervals. In one suitable arrangement, a gate driver circuit may include multiple gate line driver segments each of which is activated by a separate gate start pulse. Each gate start pulse may only be released at the end of an IFP interval. In another suitable arrangement, dummy gate driver units may be interposed among active gate driver units. Gate output signals may propagate through the dummy gate driver units during the IFP internal. In another suitable arrangement, each active gate driver unit may be provided with a buffer portion that protects at least some transistor in the gate driver unit from undesired stress.
Abstract translation: 触摸屏显示器可以包括耦合到显示像素阵列的栅极线驱动器电路。 显示器可以具有帧内暂停（IFP）能力，其中可以在一个或多个帧内消隐间隔期间执行触摸或其它操作。 在一种合适的布置中，栅极驱动电路可以包括多个栅极线驱动器段，每个栅驱动器段由单独的栅极起始脉冲激活。 每个栅极起始脉冲只能在IFP间隔结束时释放。 在另一种合适的布置中，虚拟栅极驱动器单元可插入有源栅极驱动器单元中。 栅极输出信号可能在IFP内部传播通过虚拟栅极驱动器单元。 在另一种合适的布置中，每个有源栅极驱动器单元可以设置有缓冲部分，其保护栅极驱动器单元中的至少一些晶体管免受不期望的应力。
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公开(公告)号：US20130235003A1
公开(公告)日：2013-09-12
申请号：US13661839
申请日：2012-10-26
Applicant: APPLE INC.
Inventor： Shih Chang Chang , Young Bae Park , Chun-Yao Huang , Kyung Wook Kim , Szu-Hsien Lee
IPC: G06F3/038
CPC classification number: G09G3/3677
Abstract: Gate line driver circuitry applies an output pulse to each of several gate lines for a display element array. The circuitry has a number of gate drivers each being coupled to drive a respective one of the gate lines. Each of the gate drivers has an output stage in which a high side transistor and a low side transistor are coupled to drive the respective gate line, responsive to at least one clock signal. A pull down transistor is coupled to discharge a control electrode of the output stage. A control circuit having a cascode amplifier is coupled to drive the pull down transistor as a function of a) at least one clock signal and b) feedback from the control electrode. Other embodiments are also described and claimed.
Abstract translation: 栅极线驱动器电路将输出脉冲施加到用于显示元件阵列的多个栅极线中的每一个。 电路具有多个栅极驱动器，每个栅极驱动器被耦合以驱动相应的一条栅极线。 每个栅极驱动器具有输出级，其中高侧晶体管和低侧晶体管耦合以响应于至少一个时钟信号驱动相应的栅极线。 耦合下拉晶体管以放电输出级的控制电极。 具有共源共栅放大器的控制电路被耦合以作为a）至少一个时钟信号和b）来自控制电极的反馈来驱动下拉晶体管。 还描述和要求保护其他实施例。
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Patent Agency Ranking
公开(公告)号：US20230084423A1
公开(公告)日：2023-03-16
申请号：US17853649
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Myungjoon Choi , Jie Won Ryu , Hyunwoo Nho , Xiaokai Li , Kaikai Guo , Szu-Hsien Lee , Rungrot Kitsomboonloha , Pei-En Chang , Amit Nayyar , Vehbi Calayir
Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.
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公开(公告)号：US11605330B1
公开(公告)日：2023-03-14
申请号：US17853649
申请日：2022-06-29
Applicant: Apple Inc.
Inventor： Myungjoon Choi , Jie Won Ryu , Hyunwoo Nho , Xiaokai Li , Kaikai Guo , Szu-Hsien Lee , Rungrot Kitsomboonloha , Pei-En Chang , Amit Nayyar , Vehbi Calayir
Abstract: Embodiments presented herein relate to reducing visual artifacts on an electronic display caused by an intra-frame pause. To do so, the intra-frame pause may be divided into smaller intra-frame pause segments. The intra-frame pause segments may be applied to the display during different image frames and/or at different locations on the electronic display. For example, each intra-frame pause segment may be applied to a different location on the electronic display. In some embodiments, multiple intra-frame pause segments may be applied during a single image frame. In some embodiments, the intra-frame pause segments may be applied to various image frames and at various location on the electronic display according to a pattern. To reduce band flickering that may be caused by the different locations of the intra-frame pause segments, an emission duty of one or more rows of pixels of the display may be adjusted.
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公开(公告)号：US11580905B2
公开(公告)日：2023-02-14
申请号：US17749045
申请日：2022-05-19
Applicant: Apple Inc.
Inventor： Rungrot Kitsomboonloha , Chin-Wei Lin , Shinya Ono , Gihoon Choo , Hao-Lin Chiu , Kyung Wook Kim , Pei-En Chang , Szu-Hsien Lee , Zino Lee
IPC: G09G3/3225
Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.
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公开(公告)号：US20210305353A1
公开(公告)日：2021-09-30
申请号：US17143939
申请日：2021-01-07
Applicant: Apple Inc.
Inventor： Shinya Ono , Chin-Wei Lin , Akira Matsudaira , Jiun-Jye Chang , Jung Yen Huang , Pei-En Chang , Rungrot Kitsomboonloha , Szu-Hsien Lee
IPC: H01L27/32 , G09G3/3266 , G09G3/3225
Abstract: An electronic device may include a display with pixels formed using light-emitting diodes, thin-film silicon transistors, thin-film semiconducting-oxide transistors, and capacitors. The silicon transistors, semiconducting-transistors, and capacitors may have control terminals that are coupled to gate or routing lines that extend across the face of the display and that are formed in a low resistance source-drain metal routing layer. Forming routing/gate lines using the low resistance source-drain metal routing layer dramatically reduces the resistance of the gate lines, which enables better timing margins for large display panels operating at higher refresh rates.
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公开(公告)号：US10345972B2
公开(公告)日：2019-07-09
申请号：US15179763
申请日：2016-06-10
Applicant: Apple Inc.
Inventor： Szu-Hsien Lee , Byung Duk Yang , Chun-Yao Huang , Kyung-Wook Kim , Shih-Chang Chang
Abstract: A touch screen. In some examples, the touch screen can comprise a first element coupled to a first sense connection, and a second element coupled to a second sense connection. In some examples, the first and second sense connections can be configured such that a load presented by the first sense connection and the first element is substantially equal to a load presented by the second sense connection and the second element. In some examples, the first and second sense connections can comprise detour routing configured such that a resistance of the first sense connection is substantially equal to a resistance of the second sense connection. In some examples, the first and second sense connections can be coupled to dummy routing configured such that a first capacitance presented by the first sense connection is substantially equal to a second capacitance presented by the second sense connection.
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