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21.发明申请公开(公告)号：US20160124746A1
公开(公告)日：2016-05-05
申请号：US14582968
申请日：2014-12-24
申请人： ARM Limited
IPC分类号： G06F9/30
CPC分类号： G06F7/483 , G06F5/012 , G06F7/38 , G06F7/48 , G06F7/4991 , G06F7/49915 , G06F7/49921 , G06F7/49942 , G06F7/506 , G06F7/507 , G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30025 , G06F9/30036 , G06F9/30112 , G06F9/3016 , G06F9/30185 , G06F9/30192 , G06F9/3885 , G06F11/3404 , G06F11/3476 , G06F11/348 , G06F11/3636 , G06F11/3644 , G06F11/3648 , G06F17/16 , G06F2201/865 , G06F2207/483 , H03M7/12 , H03M7/24
摘要： A data processing system supports vector operands with components representing different bit significance portions of an integer number. Processing circuitry performs a processing operation specified by a program instruction in dependence upon a number of components comprising the vector as specified by metadata for the vector.
摘要翻译： 数据处理系统支持具有表示整数的不同位重要部分的分量的向量操作数。 处理电路根据由向量的元数据指定的包括向量的多个组件来执行由程序指令指定的处理操作。
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公开(公告)号：US20160124715A1
公开(公告)日：2016-05-05
申请号：US14528326
申请日：2014-10-30
申请人： ARM LIMITED
发明人： Neil BURGESS , David Raymond LUTZ
CPC分类号： G06F7/50 , G06F7/02 , G06F7/509 , G06F7/544 , G06F7/57 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F17/16
摘要： An apparatus 8 for performing a selectable one of multi-element comparison and multi-element addition is formed from a carry propagate adders stage 12 supplied with four non-final intermediate operands formed from the input vector, a non-final limit value selecting stage 14, which when performing a multi-element comparison serves to select, in dependence upon at least carry save values generated by the carry propagate adder, limit values that are of a larger or a smaller value of a pair of elements. A final intermediate operand forming stage 16 forms final intermediate operands from two non-final intermediate sum values from the carry propagate adders stage 12 and supplies these to a final output adder stage 18 which forms a sum of these two final intermediate operands to generate an output operand which can be either one or more candidates for limit values that will be a maximum or minimum value, or a sum value, or partial sum values in the case of a multi-element addition.
摘要翻译： 从提供有由输入向量形成的四个非最终中间操作数的进位传播加法器级12形成用于执行多元素比较和多元素相加可选择的装置8，非最终极限值选择级14 其在执行多元素比较时用于根据进位传播加法器产生的至少携带保存值来选择具有一对元素的较大值或较小值的限制值。 最终的中间操作数形成级16从来自进位传播加法器级12的两个非最终中间和值形成最终中间操作数，并将其提供给最终输出加法器级18，其形成这两个最终中间操作数的和以产生输出 操作数，其可以是作为最大值或最小值的极限值的一个或多个候选者，或者是多个元素添加的情况下的和值或部分和值。
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公开(公告)号：US20160110161A1
公开(公告)日：2016-04-21
申请号：US14519787
申请日：2014-10-21
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G06F7/485
CPC分类号： G06F7/485 , G06F7/483 , G06F7/535 , G06F7/5525 , G06F7/57 , G06F2207/48 , G06F2207/5356
摘要： A data processing apparatus has floating-point add circuitry for performing a floating-point add operation for adding or subtracting two floating-point operands. The apparatus also has reciprocal estimation circuitry for performing a reciprocal estimation operation on a first operand to generate a reciprocal estimate value which represents an estimate of a reciprocal of a first operand or an estimate or a reciprocal of the square root of the first operand. The reciprocal estimation circuitry is physically distinct from the floating-point adder circuitry, which allows both the reciprocal estimate and the add operations to be faster.
摘要翻译： 数据处理装置具有用于执行用于相加或减去两个浮点操作数的浮点加法运算的浮点加法电路。 该装置还具有相互估计电路，用于对第一操作数执行倒数估计操作，以产生表示第一操作数的倒数的估计或第一操作数的平方根的倒数的倒数的倒数估计值。 相互估计电路在物理上不同于浮点加法器电路，这允许相互估计和相加操作都更快。
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公开(公告)号：US20150269981A1
公开(公告)日：2015-09-24
申请号：US14220490
申请日：2014-03-20
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G11C7/10
CPC分类号： G11C7/1078 , G06F5/01 , G06F7/49921 , G06F9/30018 , G06F9/30032 , G11C7/1084
摘要： Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.
摘要翻译： 提供了数据处理装置和数据处理方法。 移位电路响应于移位指令执行移位操作，在由移位指令指定的方向上移位输入数据值的位。 位位置指示符生成电路和比较电路与移位电路并行操作。 位位置指示符指示输入数据值中的至少一个位位置，如果移位的数据值不饱和，则该位置不能有位置位。 比较电路将位位置指示符与输入数据值进行比较，并且如果位位置指示符指示了用于保持输入数据值中的设置位的位位置的任何位，则表示饱和状态。 因此，更快地显示饱和条件。
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25.发明申请公开(公告)号：US20150261498A1
公开(公告)日：2015-09-17
申请号：US14210609
申请日：2014-03-14
申请人： ARM LIMITED
发明人： David Raymond LUTZ , Neil BURGESS
IPC分类号： G06F5/01
摘要： A data processing apparatus and method are provided for performing a shift function on a binary number. The apparatus comprises count determination circuitry for determining a number of contiguous bit positions in the binary number that have a predetermined bit value, the count determination circuitry outputting a count value indicative of the number of contiguous bit positions determined. In parallel with the operation of the count determination circuitry, coarse shifting circuitry is used to determine, for at least one predetermined number of contiguous bit positions, whether that predetermined number of contiguous bit positions within the binary number has said predetermined bit value. An initial shift operation is then performed on the binary number based on that determination in order to produce an intermediate binary number. Once the count value is available from the count determination circuitry, fine shifting circuitry then performs a further shift operation on the intermediate binary number, based on the count value output by the count determination circuitry, in order to produce the result binary number. This provides an efficient mechanism for performing a shift function on a binary number, whilst still capturing the count value from the count determination circuitry.
摘要翻译： 提供了一种用于对二进制数执行移位功能的数据处理装置和方法。 该装置包括用于确定具有预定比特值的二进制数中的连续比特位数的计数确定电路，计数确定电路输出指示所确定的连续比特位数的计数值。 与计数确定电路的操作并行，粗移位电路用于对于至少一个预定数量的连续位位置来确定二进制数中的预定数量的连续位位置是否具有所述预定位值。 然后基于该确定对二进制数执行初始移位操作，以便产生中间二进制数。 一旦从计数确定电路获得计数值，微移位电路然后基于计数确定电路输出的计数值对中间二进制数执行进一步的移位操作，以便产生结果二进制数。 这提供了用于在二进制数字上执行移位函数同时仍从计数确定电路捕获计数值的有效机构。
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公开(公告)号：US20230305805A1
公开(公告)日：2023-09-28
申请号：US17700911
申请日：2022-03-22
申请人： Arm Limited
CPC分类号： G06F7/5443 , G06F7/485 , G06F7/487 , G06F9/30145 , G06F9/3893
摘要： Apparatus, method and non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus. The apparatus comprises instruction decode circuitry to decode instructions and processing circuitry to execute the instructions decoded by the instruction decode circuitry. The processing circuitry comprises chained-floating-point-multiply-accumulate circuitry responsive to a chained-floating-point-multiply-accumulate instruction decoded by the instruction decoder, the chained-floating-point-multiply-accumulate instruction specifying a first floating-point operand, a second floating-point operand and a third floating-point operand, to: generate an unrounded product based on multiplying the first floating-point operand and the second floating-point operand; generate a first rounding increment based on the unrounded product; generate a sum based on adding the unrounded product, a value based on the first rounding increment, and the third floating-point operand; determine a second rounding increment based on the sum; and perform rounding based on the second rounding increment.
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公开(公告)号：US20180157463A1
公开(公告)日：2018-06-07
申请号：US15370212
申请日：2016-12-06
申请人： ARM Limited
发明人： David Raymond LUTZ
摘要： A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. The intermediate value includes a number of leading 0s indicative of a prediction of a number of leading 0s in a difference between absolute values of the first floating point number and the second floating point number. The prediction differs by at most one from the number of leading 0s in the difference between absolute values of the first floating point number and the second floating point number. Count circuitry counts the number of leading 0s in said intermediate value and mask generation circuitry produces one or more masks using the intermediate value. The mask generation circuitry produces the one or more masks at the same time or before the count circuitry counts the number of leading 0s in the intermediate value.
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公开(公告)号：US20180067721A1
公开(公告)日：2018-03-08
申请号：US15258051
申请日：2016-09-07
申请人： ARM Limited
发明人： David Raymond LUTZ
CPC分类号： G06F7/485 , G06F5/01 , G06F2205/00 , G06F2207/483
摘要： A floating point adder includes leading zero anticipation circuitry 18 to determine a number of leading zeros within a result significand value of a sum of a first floating point operand and a second floating point operand. This number of leading zeros is used to generate a mask which in turn selects input bits from a non-normalized significand produced by adding the first significand value and the second significand value. The non-normalized significand is then normalized at the same time as the output rounding bits used to round the normalized significand value are generated by rounding bit generation circuitry 40.
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公开(公告)号：US20170139676A1
公开(公告)日：2017-05-18
申请号：US14939371
申请日：2015-11-12
申请人： ARM LIMITED
CPC分类号： G06F7/483 , G06F7/02 , G06F7/499 , G06F9/30014 , G06F9/30036 , G06F9/30192 , G06F9/3887 , G06F2207/483
摘要： Processing circuitry performs a plurality of lanes of processing on respective data elements of at least one operand vector to generate corresponding result data elements of a result vector. The processing circuitry identifies lane position information for each lane of processing, the lane position information for a given lane identifying a relative position of the corresponding result data element to be generated by the given lane within a corresponding result data value spanning one or more result data elements of the result vector. The processing circuitry is configured to perform each lane of processing in dependence on the lane position information identified for that lane. This enables generation of results which are wider or narrower than the vector size supported in hardware.
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公开(公告)号：US20170090869A1
公开(公告)日：2017-03-30
申请号：US14865359
申请日：2015-09-25
申请人： ARM LIMITED
发明人： David Raymond LUTZ
CPC分类号： G06F7/4876 , G06F5/012
摘要： An apparatus and method for floating-point multiplication are provided. Two partial products are generated from two operand significands, which are then added to generate a product significand. The value of an unbiased result exponent is determined from the operand exponent values and leading zero counts, and a shift amount and direction for the product significand are determined in dependence on a predetermined minimum exponent value of a predetermined canonical format. The product significand is shifted by the shift amount in the shift direction. An overflow mask identifying an overflow bit position of the product significand is generated by right shifting a predetermined mask pattern by the shift amount, and the overflow mask is applied to the product significand to extract an overflow value at the overflow bit position. This extraction of the overflow value happens before the shift circuitry shifts the product significand, allowing an overall faster floating-point multiplication to be performed.
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