公开(公告)号：US20200241589A1

公开(公告)日：2020-07-30

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US09990292B2

公开(公告)日：2018-06-05

申请号：US15196266

申请日：2016-06-29

Applicant: ARM Limited

Inventor： Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0831 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F2212/1032 ,  G06F2212/6042

Abstract: A data processing system includes a snoop filter organized as a number of lines, each storing an address tag associated with the address of data stored in one or more caches of the system, a coherency state of the data, and presence data. A snoop controller sends snoop messages in response to data access requests. The presence data is configurable in a first format, in which the value of a bit in the presence data is indicative of a subset of the nodes for which at least one node in the subset has a copy of the data in its local cache, and in a second format, in which the presence data comprises a unique identifier of a node having a copy of the data in its local cache. The snoop controller sends snoop messages to the nodes indicated by the presence data.

公开(公告)号：US09639470B2

公开(公告)日：2017-05-02

申请号：US14468536

申请日：2014-08-26

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831

CPC classification number: G06F12/0833 ,  G06F12/0831 ,  G06F2212/1016

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

公开(公告)号：US11573918B1

公开(公告)日：2023-02-07

申请号：US17380112

申请日：2021-07-20

Applicant: Arm Limited

Inventor： Mark David Werkheiser ,  Sai Kumar Marri ,  Lauren Elise Guckert ,  Gurunath Ramagiri ,  Jamshed Jalal

IPC: G06F13/14 ,  G06F13/40

Abstract: Aspects of the present disclosure relate to an interconnect comprising interfaces to communicate with respective requester and receiver node devices, and home nodes. Each home node is configured to: receive requests from one or more requester nodes, each request comprising a target address corresponding to a target receiver nodes; and transmit each said request to the corresponding target receiver node. Mapping circuitry is configured to: associate each of said plurality of home nodes with a given home node cluster; perform a first hashing of the target address of a given request, to determine a target cluster; perform a second hashing of the target address, to determine a target home node within said target cluster; and direct the given message, to the target home node.

公开(公告)号：US20220308997A1

公开(公告)日：2022-09-29

申请号：US17212804

申请日：2021-03-25

Applicant: Arm Limited

Inventor： Kishore Kumar Jagadeesha ,  Jamshed Jalal ,  Tushar P Ringe ,  Mark David Werkheiser ,  Premkishore Shivakumar ,  Lauren Elise Guckert

IPC: G06F12/0815 ,  G06F13/40

Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.

公开(公告)号：US20220164288A1

公开(公告)日：2022-05-26

申请号：US17102997

申请日：2020-11-24

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Jamshed Jalal ,  Mark David Werkheiser ,  Tushar P. Ringe ,  Mukesh Patel ,  Sakshi Verma

IPC: G06F12/0815

Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.

公开(公告)号：US10802534B2

公开(公告)日：2020-10-13

申请号：US16256675

申请日：2019-01-24

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/10 ,  G06F1/08 ,  H03L7/091 ,  H03L7/081 ,  G06F1/24

Abstract: Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.

公开(公告)号：US20200301854A1

公开(公告)日：2020-09-24

申请号：US16361728

申请日：2019-03-22

Applicant: Arm Limited

Inventor： Gurunath Ramagiri ,  Tushar P. Ringe ,  Mukesh Patel ,  Jamshed Jalal ,  Ashok Kumar Tummala ,  Mark David Werkheiser

IPC: G06F12/14 ,  G06F12/0817 ,  G06F9/54

Abstract: A system, apparatus and method for protecting coherent memory contents in a coherent data processing network by filtering data access requests and snoop response based on the Read/Write (R/W) access permissions. Requests are augmented with access permissions in memory protection units and the access permissions are used to control memory access by home nodes of the network.

公开(公告)号：US10591977B2

公开(公告)日：2020-03-17

申请号：US14965184

申请日：2015-12-10

Applicant: ARM Limited

Inventor： Mark David Werkheiser ,  Dominic William Brown ,  Ashley John Crawford ,  Paul Gilbert Meyer

IPC: G06F1/32 ,  G06F1/3234 ,  G06F12/0813 ,  G06F12/0831

Abstract: A method, system, and device provide for selective control in a distributed cache system of the power state of a number of receiver partitions arranged in one or more partition groups. A power control element coupled to one or more of the receiver partitions and a coherent interconnect selectively control transition from a current power state to a new power state by each receiver partition of one or more partition groups of the plurality of partition groups.

公开(公告)号：US10585449B1

公开(公告)日：2020-03-10

申请号：US16248456

申请日：2019-01-15

Applicant: Arm Limited

Inventor： Tushar P. Ringe ,  Ramamoorthy Guru Prasadh ,  Amaresh Pangal ,  Kishore Kumar Jagadeesha ,  Mark David Werkheiser

IPC: G06F1/04 ,  G06F1/10 ,  H03L7/099

Abstract: Various implementations described herein refer to an integrated circuit having a clock generator providing a clock signal. The integrated circuit may include a block having a block boundary, and the block receives the clock signal from the clock generator and provides the clock signal along a clock-tree. The integrated circuit may include a plurality of sub-blocks disposed within the block boundary of the block, and each sub-block of the plurality of sub-blocks receives the clock signal from within the block boundary of the block via the clock-tree, and diverges the clock signal into a first clock signal and a second clock signal from within a sub-block boundary of each sub-block.