公开(公告)号：US20220382679A1

公开(公告)日：2022-12-01

申请号：US17331806

申请日：2021-05-27

Applicant: Arm Limited

Inventor： Jamshed Jalal ,  Bruce James Mathewson ,  Tushar P Ringe ,  Sean James Salisbury ,  Antony John Harris

IPC: G06F12/0815 ,  G06F12/0895

Abstract: The present disclosure advantageously provides a system cache and a method for storing coherent data and non-coherent data in a system cache. A transaction is received from a source in a system, the transaction including at least a memory address, the source having a location in a coherent domain or a non-coherent domain of the system, the coherent domain including shareable data and the non-coherent domain including non-shareable data. Whether the memory address is stored in a cache line is determined, and, when the memory address is not determined to be stored in a cache line, a cache line is allocated to the transaction including setting a state bit of the allocated cache line based on the source location to indicate whether shareable or non-shareable data is stored in the allocated cache line, and the transaction is processed.

公开(公告)号：US11314676B2

公开(公告)日：2022-04-26

申请号：US14944340

申请日：2015-11-18

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F13/40 ,  G06F12/0815 ,  G06F13/16 ,  G06F13/42

Abstract: There is provided an interconnect for transferring requests between ports in which the ports include both source ports destination ports. The interconnect includes storage circuitry for storing the requests. Input circuitry receives the requests from the plurality of source ports, selects at least one selected source port from an allowed set of said plurality of source ports, and transfers a presented request from the at least one selected source port to the storage circuitry. Output circuitry causes a request in said storage circuitry to be output at one of said plurality of destination ports. Counter circuitry maintains counter values for a plurality of tracked ports from amongst said ports, each counter value indicating the number of requests in said storage circuitry associated with a corresponding tracked port that are waiting to be output by said output circuitry and filter circuitry determines whether or not a given source port is in said allowed set in dependence on said counter circuitry.

公开(公告)号：US09977742B2

公开(公告)日：2018-05-22

申请号：US15133311

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Sean James Salisbury

IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/12

CPC classification number: G06F12/0817 ,  G06F12/0833 ,  G06F12/12 ,  G06F2212/1016

Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by a group of two or more cache memories in a coherent cache structure, which of the cache memories are caching those memory addresses, the directory being associative so that multiple memory addresses map to an associative set of more than one directory entry; and control logic responsive to a memory address to be newly cached, and configured to detect whether one or more of the set of directory entries mapped to that memory address is available for storage of an indication of which of the two or more cache memories are caching that memory address; the control logic being configured so that when all of the set of directory entries mapped to that memory address are occupied, the control logic is configured to select one of the set of directory entries as a directory entry to be overwritten and the corresponding cached information to be invalidated, the control logic being configured to select a directory entry to be overwritten, from the set of directory entries, in dependence upon which of the group of two or more cache memories is indicated by that directory entry, according to a likelihood of selection amongst the two or more cache memories.

公开(公告)号：US09852088B2

公开(公告)日：2017-12-26

申请号：US14628331

申请日：2015-02-23

Applicant: ARM LIMITED

Inventor： Andrew David Tune ,  Daniel Sara ,  Sean James Salisbury ,  Arthur Laughton ,  Peter Andrew Riocreux

IPC: G06F13/16 ,  G06F13/00

CPC classification number: G06F13/1626 ,  G06F13/1673

Abstract: A system-on-check integrated circuit 2 includes interconnect circuitry 4 connecting a plurality of transaction sources to a plurality of transaction destinations. The interconnect circuitry 4 includes a reorder buffer for buffering access transactions and hazard checking circuitry 46, 48, 50, 52 for performing hazard checks, such as point-of-serialization checks and identifier reuse checks. Check suppression circuitry 62, 64, 66, 68 serves to suppress one or more hazard checks depending upon one or more state variables that themselves depend upon access transactions other than the access transaction for which the hazard checking is or is not to be suppressed. As an example, hazard checking may be suppressed if it is known that there are no other access transactions currently buffered within the reorder buffer 26 or alternatively no other access transactions from the same transaction source buffered within the reorder buffer 26.

公开(公告)号：US09639470B2

公开(公告)日：2017-05-02

申请号：US14468536

申请日：2014-08-26

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Jamshed Jalal ,  Mark David Werkheiser

IPC: G06F12/08 ,  G06F12/0831

CPC classification number: G06F12/0833 ,  G06F12/0831 ,  G06F2212/1016

Abstract: An interconnect has coherency control circuitry for performing coherency control operations and a snoop filter for identifying which devices coupled to the interconnect have cached data from a given address. When an address is looked up in the snoop filter and misses, and there is no spare snoop filter entry available, then the snoop filter selects a victim entry corresponding to a victim address, and issues an invalidate transaction for invalidating locally cached copies of the data identified by the victim. The coherency control circuitry for performing coherency checking operations for data access transactions is reused for performing coherency control operations for the invalidate transaction issued by the snoop filter. This greatly reduces the circuitry complexity of the snoop filter.

公开(公告)号：US09311244B2

公开(公告)日：2016-04-12

申请号：US14467469

申请日：2014-08-25

Applicant: ARM LIMITED

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Daniel Sara

IPC: G06F12/02 ,  G06F12/08

CPC classification number: G06F12/0831 ,  G06F2212/1016 ,  G06F2212/621

Abstract: An interconnect has transaction tracking circuitry for enforcing ordering of a set of data access transactions so that they are issued to slave devices in an order in which they are received from master devices. The transaction tracking circuitry is reused for also enforcing ordering of snoop transactions which are triggered by the set of data access transactions, for snooping master devices identified by a snoop filter as holding cache data for the target address of the transactions.

Abstract translation: 互连具有用于实施一组数据访问事务的排序的事务跟踪电路，使得它们以从主设备接收的顺序被发布到从设备。 交易跟踪电路被重新用于执行由一组数据访问事务触发的窥探事务的排序，用于窥探由窥探过滤器识别的主设备作为事务的目标地址的缓存数据。

公开(公告)号：US09213660B2

公开(公告)日：2015-12-15

申请号：US13918025

申请日：2013-06-14

Applicant: ARM Limited

Inventor： Sean James Salisbury ,  Andrew David Tune ,  Alistair Crone Bruce

IPC: G06F13/00 ,  G06F13/362

CPC classification number: G06F13/362 ,  G06F13/37

Abstract: A data processing apparatus is provided with a master device and a slave device which communicate via communication circuitry. The slave device is associated with a predetermined number of permission tokens that is equal to a maximum number of currently pending messages that can be accepted for processing from the communication circuitry by that slave device. The slave device transmits these permission tokens to the master device. The master device takes exclusive temporary possession of the permission tokens that it receives such that the permission tokens are then no longer available to any other master device. A master device initiates a message to a slave device when the master device has exclusive temporary possession of a permission token for that slave device. When the master device has initiated its message, then it relinquishes the exclusive temporary possession of the permission token such that it is then available for other devices.

Abstract translation: 数据处理装置具有通过通信电路进行通信的主设备和从设备。 从设备与预定数量的权限令牌相关联，该权限令牌等于可由该从设备从通信电路接受用于处理的当前待定消息的最大数量。 从设备将这些权限令牌发送到主设备。 主设备占用其接收到的权限令牌的专属临时占用，使得许可令牌不再可用于任何其他主设备。 当主设备对该从设备具有独占临时拥有权限令牌时，主设备向从设备发起消息。 当主设备已经发起其消息时，它放弃对该权限令牌的独占临时拥有，使得其可用于其他设备。

公开(公告)号：US20140372696A1

公开(公告)日：2014-12-18

申请号：US13920685

申请日：2013-06-18

Applicant: ARM Limited

Inventor： Andrew David TUNE ,  Sean James Salisbury

IPC: G06F3/06

CPC classification number: G06F12/0864 ,  G06F12/0846

Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

Abstract translation: 数据阵列有多种方式，每种方式都有用于存储数据值的条目。 响应于写请求，具有目标地址的更新的数据值可以存储在包括从每个方式基于目标地址选择的条目的对应的一组条目中的任何一个中。 更新队列存储表示待决写入请求的更新信息。 对于与不同方式相对应的一组待决写入请求，从更新队列中选择更新信息，并且并行执行这些写入请求，使得更新的值被写入不同方式的条目。