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    Circuitry and method
    1.
    发明授权
    Circuitry and method 有权

    公开(公告)号：US12174738B2

    公开(公告)日：2024-12-24

    申请号：US17885780

    申请日：2022-08-11

    Applicant: Arm Limited

    Inventor： Andrew David Tune ,  Sean James Salisbury ,  Edward Martin McCombs, Jr.

    IPC: G06F12/0802

    Abstract: Circuitry including cache storage and control circuitry is provided. The cache storage includes an array of random access memory storage elements, and is configured to store data in multiple cache sectors, each cache sector including a number of cache storage data units. The control circuitry is configured to control access to the cache storage including, for example, accessing the cache storage data units in the cache sectors. After accessing a cache storage data unit in a cache sector, the energy requirement and/or latency for the next access to a cache storage data unit in the same sector is lower than the energy requirement and/or latency for the next access to a cache storage data unit in a different same sector.

    Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location
    2.
    发明授权
    Interconnection network for integrated circuit with fault detection circuitry provided locally to an upstream location 有权

    公开(公告)号：US10938622B2

    公开(公告)日：2021-03-02

    申请号：US16423386

    申请日：2019-05-28

    Applicant: Arm Limited

    Inventor： Julian Jose Hilgemberg Pontes ,  Andrew David Tune ,  Sean James Salisbury

    IPC: H04L12/24 ,  H04L12/46

    Abstract: An interconnection network is provided for managing data transfer between a plurality of nodes of an integrated circuit. The interconnection network has at least one transmission path originating from an upstream location of the interconnection network, each transmission path being arranged to transmit data blocks from the upstream location to an associated downstream location within that transmission path. Digest generation circuitry is used to generate digests for data blocks, and fault detection circuitry provided in association with the upstream location is arranged to determine presence of a fault condition in the interconnection network. The digest generation circuitry is arranged to generate an upstream digest for a given data block at the upstream location, and to generate a corresponding downstream digest for the given data block at the associated downstream location. The fault detection circuitry is arranged to receive upstream digests from the upstream location and corresponding downstream digests received via a return path from each downstream location, and to determine presence of the fault condition based on a comparison of each upstream digest with its corresponding downstream digest.

    Relative data width indication for read responses routed by an interconnect
    3.
    发明授权
    Relative data width indication for read responses routed by an interconnect 有权

    公开(公告)号：US10437750B2

    公开(公告)日：2019-10-08

    申请号：US15850296

    申请日：2017-12-21

    Applicant: Arm Limited

    Inventor： Arthur Brian Laughton ,  Sean James Salisbury ,  Chiranjeev Acharya ,  Eduard Vardanyan

    IPC: G06F13/12 ,  G06F13/16 ,  G06F13/42

    Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.

    Interconnect and method of handling supplementary data in an interconnect
    4.
    发明授权
    Interconnect and method of handling supplementary data in an interconnect 有权

    公开(公告)号：US10565146B2

    公开(公告)日：2020-02-18

    申请号：US15859830

    申请日：2018-01-02

    Applicant: Arm Limited

    Inventor： Andrew Brian Thomas Hopkins ,  Sean James Salisbury

    IPC: G06F11/00 ,  G06F13/40 ,  H04L1/00 ,  G06F13/00 ,  G06F11/07 ,  G06F13/16 ,  H04L5/00

    Abstract: An interconnect, and method of handling supplementary data in an interconnect, are provided. The interconnect has routing circuitry providing a plurality of paths, and routing control circuitry to use the plurality of paths to establish routes through the interconnect between source devices and destination devices coupled to the interconnect, to enable system data to be routed through the interconnect between the source devices and the destination devices. The system data relates to functional operation of a system comprising the interconnect, the source devices and the destination devices. At least a subset of the paths are redundant paths whose use by the routing control circuitry provides the system data with resilience to faults when routing the system data through the interconnect. The routing control circuitry is responsive to supplementary data which is unnecessary to ensure the functional operation of the system, to establish a supplementary data route through the interconnect to a supplementary data receiving circuit, such that the supplementary data route employs at least one of the redundant paths that is not required to provide resilience for the system data at a time the at least one of the redundant paths is used for the supplementary data route. This provides an efficient mechanism for transporting supplementary data, whilst ensuring non-intrusive behaviour.

    Interconnect and method of managing a snoop filter for an interconnect
    6.
    发明授权
    Interconnect and method of managing a snoop filter for an interconnect 有权

    公开(公告)号：US09727466B2

    公开(公告)日：2017-08-08

    申请号：US14822953

    申请日：2015-08-11

    Applicant: ARM LIMITED

    Inventor： Andrew David Tune ,  Sean James Salisbury

    IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0808

    CPC classification number: G06F12/0833 ,  G06F12/0808 ,  G06F12/0831 ,  G06F2212/62 ,  G06F2212/621 ,  Y02D10/13

    Abstract: An interconnect and method of managing a snoop filter within such an interconnect are provided. The interconnect is used to connect a plurality of devices, including a plurality of master devices where one or more of the master devices has an associated cache storage. The interconnect comprises coherency control circuitry to perform coherency control operations for data access transactions received by the interconnect from the master devices. In performing those operations, the coherency control circuitry has access to snoop filter circuitry that maintains address-dependent caching indication data, and is responsive to a data access transaction specifying a target address to produce snoop control data providing an indication of which master devices have cached data for the target address in their associated cache storage. The coherency control circuitry then responds to the snoop control data by issuing a snoop transaction to each master device indicated by the snoop control data, in order to cause a snoop operation to be performed in their associated cache storage in order to generate snoop response data. Analysis circuitry then determines from the snoop response data an update condition, and upon detection of the update condition triggers performance of an update operation within the snoop filter circuitry to update the address-dependent caching indication data. By subjecting the snoop response data to such an analysis, it is possible to identify situations where the caching indication data has become out of date, and update that caching indication data accordingly, this giving rise to significant performance benefits in the operation of the interconnect.

    Handling write requests for a data array
    7.
    发明授权
    Handling write requests for a data array 有权
    处理数据数组的写请求

    公开(公告)号：US09361236B2

    公开(公告)日：2016-06-07

    申请号：US13920685

    申请日：2013-06-18

    Applicant: ARM Limited

    Inventor： Andrew David Tune ,  Sean James Salisbury

    IPC: G06F12/08

    CPC classification number: G06F12/0864 ,  G06F12/0846

    Abstract: A data array has multiple ways, each way having entries for storing data values. In response to a write request, an updated data value having a target address may be stored in any of a corresponding set of entries comprising an entry selected from each way based on the target address. An update queue stores update information representing pending write requests. Update information is selected from the update queue for a group of pending write requests corresponding to different ways, and these write requests are performed in parallel so that updated values are written to entries of different ways.

    Abstract translation: 数据阵列有多种方式，每种方式都有用于存储数据值的条目。 响应于写请求，具有目标地址的更新的数据值可以存储在包括从每个方式基于目标地址选择的条目的对应的一组条目中的任何一个中。 更新队列存储表示待决写入请求的更新信息。 对于与不同方式相对应的一组待决写入请求，从更新队列中选择更新信息，并且并行执行这些写请求，使得更新的值被写入不同方式的条目。

    Integrated circuit design and fabrication
    9.
    发明授权
    Integrated circuit design and fabrication 有权

    公开(公告)号：US10796040B2

    公开(公告)日：2020-10-06

    申请号：US16267498

    申请日：2019-02-05

    Applicant: Arm Limited

    Inventor： Sean James Salisbury ,  Zheng Xu ,  Arthur Brian Laughton ,  Charles Filip Brej

    IPC: G06F30/30 ,  G06F30/394 ,  G06F30/398 ,  G06F9/30

    Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second routing.

    Cache coherency
    10.
    发明授权
    Cache coherency 有权

    公开(公告)号：US10169236B2

    公开(公告)日：2019-01-01

    申请号：US15133341

    申请日：2016-04-20

    Applicant: ARM LIMITED

    Inventor： Sean James Salisbury ,  Andrew David Tune

    IPC: G06F12/08 ,  G06F12/0817 ,  G06F12/0813

    Abstract: A cache coherency controller comprises a directory indicating, for memory addresses cached by one or more of a group of one or more cache memories connectable in a coherent cache structure, which of the cache memories are caching those memory addresses; and control circuitry configured to detect a directory entry relating to a memory address to be accessed so as to coordinate, amongst the cache memories, an access to a memory address by one of the cache memories or a coherent agent in instances when the directory entry indicates that another of the cache memories is caching that memory address; the control circuitry being responsive to status data indicating whether each cache memory in the group is currently subject to cache coherency control so as to take into account, in the detection of the directory entry relating to the memory address to be accessed, only those cache memories in the group which are currently subject to cache coherency control.

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