公开(公告)号：US20180150297A1

公开(公告)日：2018-05-31

申请号：US15578324

申请日：2016-03-31

Applicant: ARM LIMITED

Inventor： Max John BATLEY ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F1/32

CPC classification number: G06F9/30145 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3885

Abstract: An apparatus (2) has a processing pipeline (4) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure (22, 30, 36, 50, 40, 64, 44) is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry (70) triggers a subset (102) of the entries of the storage structure to be placed in a power saving state.

公开(公告)号：US20170329603A1

公开(公告)日：2017-11-16

申请号：US15666978

申请日：2017-08-02

Applicant: ARM Limited

Inventor： Simon John CRASKE ,  Richard Roy GRISENTHWAITE ,  Nigel John STEPHENS

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: An apparatus performs an operation on a register, and then conditionally selects either that register or a further register on which no operation has been performed. The apparatus includes a decoder that decodes a conditional select instruction that specifies a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register. A data processor is responsive to the decoded conditional select instruction and the condition (i) having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register, and (ii) not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

公开(公告)号：US20160357561A1

公开(公告)日：2016-12-08

申请号：US15097377

申请日：2016-04-13

Applicant: ARM LIMITED

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30083 ,  G06F9/30058 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3867

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

Abstract translation: 处理管线可以具有具有不同性能或能量消耗特性的第一和第二执行电路。 指令供应电路可以支持具有不同能量消耗或性能特征的不同指令供给方案。 这可以在性能和能源效率之间进一步权衡。 建筑状态存储可以在执行单元之间共享，以减少单元之间切换的开销。 在并行执行模式中，可以在两个执行单元上并行执行指令组。

公开(公告)号：US20160139922A1

公开(公告)日：2016-05-19

申请号：US14930920

申请日：2015-11-03

Applicant: ARM LIMITED

Inventor： Simon John CRASKE ,  Alexander Alfred Hornung ,  Max John BATLEY ,  Kauser Yakub JOHAR

IPC: G06F9/30 ,  G06F9/455

CPC classification number: G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/45533 ,  G06F9/522

Abstract: Apparatus for data processing and a method of data processing are provided, according to which the processing circuitry of the apparatus can access a memory system and execute data processing instructions in one context of multiple contexts which it supports. When the processing circuitry executes a barrier instruction, the resulting access ordering constraint may be limited to being enforced for accesses which have been initiated by the processing circuitry when operating in an identified context, which may for example be the context in which the barrier instruction has been executed. This provides a separation between the operation of the processing circuitry in its multiple possible contexts and in particular avoids delays in the completion of the access ordering constraint, for example relating to accesses to high latency regions of memory, from affecting the timing sensitivities of other contexts.

Abstract translation: 提供了用于数据处理的装置和数据处理方法，根据该装置，该装置的处理电路可以访问存储器系统并在其支持的多个上下文的一个上下文中执行数据处理指令。 当处理电路执行屏障指令时，所得到的访问排序约束可以被限制为对于在所识别的上下文中操作时由处理电路启动的访问被强制执行，其可以例如是屏障指令具有的上下文 被执行 这提供了处理电路在其多个可能上下文中的操作之间的间隔，并且特别地避免了访问排序约束的完成中的延迟，例如涉及对存储器的高等待时间区域的访问，从而影响其他上下文的定时灵敏度 。

公开(公告)号：US20160070630A1

公开(公告)日：2016-03-10

申请号：US14824299

申请日：2015-08-12

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  Simon John CRASKE

IPC: G06F11/26 ,  G06F11/22

CPC classification number: G06F11/26 ,  G06F9/30189 ,  G06F11/2236 ,  G06F11/3648

Abstract: A data processing apparatus has a debug state in which processing circuitry 105 executes instructions received from the debug interface 115. Control changing circuitry 135 prohibits the execution of instructions in a predefined privilege mode when in the debug state if a control parameter has a predefined value. In response to a first exception being signalled while in the debug state, where the first exception is intended to be handled at the predefined privilege mode, and further in response to the control parameter having the predefined value, signalling circuitry 115 signals a second exception to be handled at a different privilege mode from the predefined privilege mode and sets information identifying a type of the first exception. Consequently, without having to enter the prohibited (predefined) privilege mode, the debugger 110 can be made aware of the first exception that would ordinarily be handled at the predefined, i.e. prohibited privilege mode.

Abstract translation: 数据处理装置具有调试状态，其中处理电路105执行从调试接口115接收到的指令。控制改变电路135在控制参数具有预定值时处于调试状态时禁止执行预定义特权模式中的指令。 响应于在处于调试状态时发信号通知的第一异常，其中第一异常旨在以预定义的权限模式被处理，并且还响应于具有预定值的控制参数，信令电路115向第二异常发出第二异常 在与预定义的权限模式不同的特权模式下处理，并设置标识第一个异常类型的信息。 因此，无需进入禁止（预定义）特权模式，调试器110可以被认识到通常在预定义的即禁止的特权模式下处理的第一个异常。

公开(公告)号：US20230236987A1

公开(公告)日：2023-07-27

申请号：US17907178

申请日：2021-03-08

Applicant: ARM LIMITED

Inventor： Yuval ELAD ,  Richard Roy GRISENTHWAITE ,  Jason PARKER ,  Simon John CRASKE ,  Alexander Donald Charles CHADWICK

IPC: G06F12/10 ,  G06F3/06

CPC classification number: G06F12/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: Apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

公开(公告)号：US20210216244A1

公开(公告)日：2021-07-15

申请号：US17056944

申请日：2019-05-02

Applicant: Arm Limited

Inventor： Simon John CRASKE

IPC: G06F3/06 ,  G06F11/10

Abstract: An apparatus and method are provided for triggering action performance. One example apparatus comprises memory access circuitry to retrieve a data value from a memory location of a memory. The apparatus further comprises action triggering circuitry to determine whether the data value is to be interpreted according to a first interpretation or a second interpretation and, when it is determined that the data value is to be interpreted according to the second interpretation, determine whether the data value defines an action to be performed. When it is determined that the data value defines an action to be performed, the action triggering circuitry is to trigger performance of the action.

公开(公告)号：US20210157592A1

公开(公告)日：2021-05-27

申请号：US17096014

申请日：2020-11-12

Applicant: Arm Limited

Inventor： John Michael HORLEY ,  Simon John CRASKE

IPC: G06F9/30

Abstract: Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.

公开(公告)号：US20210090677A1

公开(公告)日：2021-03-25

申请号：US16578754

申请日：2019-09-23

Applicant: Arm Limited

Inventor： Simon John CRASKE

IPC: G11C29/38 ,  G06F9/30

Abstract: An apparatus and method are provided for executing debug instructions. The apparatus has processing circuitry for executing instructions fetched from memory, and a debug interface. The processing circuitry is responsive to a halt event to enter a halted mode where the processing circuitry stops executing the instructions fetched from memory, and instead is arranged to execute debug instructions received from a debugger via the debug interface. The processing circuitry is responsive to detection of a trigger condition when executing a given debug instruction to exit the halted mode transparently to the debugger, and to take an exception in order to execute exception handler code comprising a sequence of instructions fetched from memory. On return from the exception, the processing circuitry then re-enters the halted mode and performs any additional processing required to complete execution of the given debug instruction. This provides a mechanism for allowing an apparatus to perform operations required by debug instructions in situations where the processing circuitry hardware is not able to natively perform those operations in response to the specified debug instruction.

公开(公告)号：US20180088951A1

公开(公告)日：2018-03-29

申请号：US15571915

申请日：2016-04-11

Applicant: Arm Limited

Inventor： Antony John PENTON ,  Simon John CRASKE ,  Vladimir VASEKIN

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/3005 ,  G06F9/30076 ,  G06F9/30189 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3889

Abstract: Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.