公开(公告)号：US09417816B2

公开(公告)日：2016-08-16

申请号：US14146618

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F13/14 ,  G06F13/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673 ,  G06F13/16 ,  Y02D10/14

Abstract: A memory device receives a plurality of read commands and/or write commands in parallel. The memory device transmits data corresponding to respective read commands on respective portions of a data bus and receives data corresponding to respective write commands on respective portions of the data bus. The memory device includes I/O logic to receive the plurality of read commands in parallel, to transmit the data corresponding to the respective read commands on respective portions of the data bus, and to receive the data corresponding to the respective write commands on respective portions of the data bus.

Abstract translation: 存储器装置并行地接收多个读取命令和/或写入命令。 存储器件在数据总线的相应部分上发送与各个读取命令对应的数据，并且在数据总线的相应部分上接收对应于各个写命令的数据。 存储器件包括并行接收多个读取命令的I / O逻辑，以在数据总线的相应部分上发送对应于相应读取命令的数据，并且在相应部分上接收对应于各个写入命令的数据 的数据总线。

公开(公告)号：US12124373B2

公开(公告)日：2024-10-22

申请号：US18185058

申请日：2023-03-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Roberts

IPC: G06F12/08 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0862

CPC classification number: G06F12/0848 ,  G06F12/0815 ,  G06F12/0862 ,  G06F2212/282 ,  G06F2212/602 ,  G06F2212/621

Abstract: A method and apparatus physically partitions clean and dirty cache lines into separate memory partitions, such as one or more banks, so that during low power operation, a cache memory controller reduces power consumption of the cache memory containing the clean only data. The cache memory controller controls refresh operation so that data refresh does not occur for clean data only banks or the refresh rate is reduced for clean data only banks. Partitions that store dirty data can also store clean data, however other partitions are designated for storing only clean data so that the partitions can have their refresh rate reduced or refresh stopped for periods of time. When multiple DRAM dies or packages are employed, the partition can occur on a die or package level as opposed to a bank level within a die.

公开(公告)号：US11748186B2

公开(公告)日：2023-09-05

申请号：US17712380

申请日：2022-04-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Andrew G. Kegel ,  David A. Roberts

IPC: G06N5/04 ,  G06N3/02 ,  G06N20/00 ,  G06F11/07 ,  G06V10/764 ,  G06V10/82

CPC classification number: G06F11/076 ,  G06F11/0706 ,  G06F11/0793 ,  G06N3/02 ,  G06N5/04 ,  G06V10/764 ,  G06V10/82 ,  G06N20/00

Abstract: A neural network runs a known input data set using an error free power setting and using an error prone power setting. The differences in the outputs of the neural network using the two different power settings determine a high level error rate associated with the output of the neural network using the error prone power setting. If the high level error rate is excessive, the error prone power setting is adjusted to reduce errors by changing voltage and/or clock frequency utilized by the neural network system. If the high level error rate is within bounds, the error prone power setting can remain allowing the neural network to operate with an acceptable error tolerance and improved efficiency. The error tolerance can be specified by the neural network application.

公开(公告)号：US20200174748A1

公开(公告)日：2020-06-04

申请号：US16206879

申请日：2018-11-30

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F7/22 ,  G06N3/04 ,  G06F16/901

Abstract: An electronic device including a neural network processor and a presorter is described. The presorter determines a sorted order to be used by the neural network processor for processing a set of instances of input data through the neural network, the determining including rearranging an initial order of some or all of the instances of input data so that instances of input data having specified similarities among the some or all of the instances of input data are located nearer to one another in the sorted order. The presorter provides, to the neural network processor, the sorted order to be used for controlling an order in which instances of input data from among the set of instances of input data are processed through the neural network. A controller in the electronic device adjusts operation of the presorter based on efficiencies of the presorter and the neural network processor.

公开(公告)号：US10515671B2

公开(公告)日：2019-12-24

申请号：US15272894

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G11C7/00 ,  G11C7/22 ,  G11C29/04

Abstract: Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.

公开(公告)号：US10452548B2

公开(公告)日：2019-10-22

申请号：US15718564

申请日：2017-09-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Roberts ,  Elliot H. Mednick

IPC: G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0891 ,  G06F12/126

Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.

公开(公告)号：US20190317832A1

公开(公告)日：2019-10-17

申请号：US15952143

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Amin Farmahini-Farahani ,  David A. Roberts

IPC: G06F9/52

Abstract: A thread holding a lock notifies a sleeping thread that is waiting on the lock that the lock holding thread is “about” to release the lock. In response to the notification, the waiting thread is woken up. While the waiting thread is woken up, the lock holding thread completes other operations prior to actually releasing the lock and then releases the lock. The notification to the waiting thread hides latency associated with waking up the waiting thread by allowing operations that wake up the waiting thread to occur while the lock holding thread is performing the other operations prior to releasing the thread.

公开(公告)号：US20190317831A1

公开(公告)日：2019-10-17

申请号：US15952149

申请日：2018-04-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts ,  Nuwan Jayasena

IPC: G06F9/52

Abstract: A memory fence or other similar operation is executed with reduced latency. An early fence operation is executed and acts as a hint to the processor executing the thread that executes the fence. This hint causes the processor to begin performing sub-operations for the fence earlier than if no such hint were executed. Examples of sub-operations for the fence include operations to make data written to by writes prior to the fence operation available to other threads. A resolving fence, which occurs after the early fence, performs the remaining sub-operations for the fence. By triggering some or all of the sub-operations for a memory fence that will occur in the future, the early fence operation reduces the amount of latency associated with that memory fence operation.

公开(公告)号：US10447273B1

公开(公告)日：2019-10-15

申请号：US16128014

申请日：2018-09-11

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Shenghsun Cho

IPC: G06F7/38 ,  H03K19/173 ,  H03K19/177 ,  G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: A method for allocating field-programmable gate array (FPGA) resources includes monitoring a first operating metric for one or more computing devices, identifying a first portion of plurality of macro components of a set of one or more FPGA devices in the one or more computing devices, where the first portion is allocated for implementing one or more user defined functions. The method also includes, in response to a first change in the first operating metric, reallocating the first portion of the macro components for implementing a system function associated with the first operating metric, and generating a first notification indicating the reallocation of the first portion.

公开(公告)号：US20190286513A1

公开(公告)日：2019-09-19

申请号：US15921489

申请日：2018-03-14

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Dean E. Gonzales

IPC: G06F11/07 ,  G06F13/376

Abstract: Techniques are provided herein for pre-emptively reinforcing one or more buses of a computing device against the effects of signal noise that could cause a reduction in signal integrity. The techniques generally include detecting an event (or “trigger”) that would tend to indicate that a reduction in signal integrity will occur, examining a reinforcement action policy and system status to determine what reinforcement action to take, and performing the reinforcement action.