公开(公告)号：US20230325313A1

公开(公告)日：2023-10-12

申请号：US18135555

申请日：2023-04-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: Disclosed is a system and method for use in a cache for suppressing modification of cache line. The system and method includes a processor and a memory operating cooperatively with a cache controller. The memory includes a coherence directory stored within a cache created to track at least one cache line in the cache via the cache controller. The processor instructs a cache controller to store a first data in a cache line in the cache. The cache controller tags the cache line based on the first data. The processor instructs the cache controller to store a second data in the cache line in the cache causing eviction of the first data from the cache line. The processor compares based on the tagging the first data and the second data and suppresses modification of the cache line based on the comparing of the first data and the second data.

公开(公告)号：US11755494B2

公开(公告)日：2023-09-12

申请号：US17514776

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/08 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0891 ,  G06F12/084

CPC classification number: G06F12/0891 ,  G06F9/30043 ,  G06F9/30047 ,  G06F12/084 ,  G06F13/1668

Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.

公开(公告)号：US11704250B2

公开(公告)日：2023-07-18

申请号：US17488206

申请日：2021-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0897 ,  G06F12/02 ,  G06F12/123 ,  G06F12/0864

CPC classification number: G06F12/0897 ,  G06F12/0246 ,  G06F12/0864 ,  G06F12/123

Abstract: Systems and methods are disclosed for maintaining insertion policies of a lower-level cache. Techniques are described for selecting, based on metadata of an evicted data block received from an upper-level cache, an insertion policy out of the insertion policies. Then, determining, based on the selected insertion policy, whether to insert the data block into the lower-level cache. If it is determined to insert, the data block is inserted into the lower-level cache according to the selected insertion policy. Techniques for dynamically updating the insertion policies of the lower-level cache are also disclosed.

公开(公告)号：US20230096814A1

公开(公告)日：2023-03-30

申请号：US17490820

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/123

Abstract: Techniques for performing cache operations are provided. The techniques include tracking re-references for cache lines of a cache, detecting that eviction is to occur, and selecting a cache line for eviction from the cache based on a re-reference indication.

公开(公告)号：US09916243B2

公开(公告)日：2018-03-13

申请号：US14522137

申请日：2014-10-23

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Walker ,  Paul J. Moyer ,  Richard M. Born ,  Eric Morton ,  David Christie ,  Marius Evers ,  Scott T. Bingham

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/0808 ,  G06F12/1045 ,  G06F12/1027 ,  G06F9/52 ,  G06F13/38 ,  G06F12/10

CPC classification number: G06F12/0808 ,  G06F9/467 ,  G06F9/526 ,  G06F12/1027 ,  G06F12/1054 ,  G06F2209/522 ,  G06F2212/621 ,  G06F2212/682 ,  G06F2212/683

Abstract: A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.