公开(公告)号：US12283537B2

公开(公告)日：2025-04-22

申请号：US17396604

申请日：2021-08-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/433 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: An electronic package is provided in the present disclosure. The electronic package comprises: a heat spreading component; a first electronic component disposed on the heat spreading component; and a second electronic component disposed on the first electronic component, wherein the second electronic component comprises an interconnection structure passing through the second electronic component and electrically connecting the first electronic component. In this way, through the use of the interconnection structure, the heat dissipation of the electronic components in the package can be improved. Also, through the use of the encapsulant, the stacked electronic components can be protected by the encapsulant so as to avoid being damaged.

公开(公告)号：US12009317B2

公开(公告)日：2024-06-11

申请号：US17321139

申请日：2021-05-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt ,  Kay Stefan Essig

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/433

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/433 ,  H01L23/49548

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.

公开(公告)号：US11791281B2

公开(公告)日：2023-10-17

申请号：US16824425

申请日：2020-03-19

Applicant: Advanced Semiconductor Engineering, Inc. ,  Phoenix Pioneer Technology Co., Ltd.

Inventor： You-Lung Yen ,  Pao-Hung Chou ,  Chun-Hsien Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

公开(公告)号：US11749619B2

公开(公告)日：2023-09-05

申请号：US16824425

申请日：2020-03-19

Applicant: Advanced Semiconductor Engineering, Inc. ,  Phoenix Pioneer Technology Co., Ltd.

Inventor： You-Lung Yen ,  Pao-Hung Chou ,  Chun-Hsien Yu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511 ,  H01L2924/35121

Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.

公开(公告)号：US11735433B2

公开(公告)日：2023-08-22

申请号：US17213033

申请日：2021-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L21/48 ,  H01L23/66 ,  H01L23/498 ,  H01Q1/22 ,  H01L23/552 ,  H01L23/14 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/4803 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/552 ,  H01L23/66 ,  H01Q1/2283 ,  H01L23/142 ,  H01L24/16 ,  H01L2223/6677 ,  H01L2224/16227

Abstract: A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.

公开(公告)号：US11664339B2

公开(公告)日：2023-05-30

申请号：US16854730

申请日：2020-04-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L21/683

CPC classification number: H01L24/20 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/19 ,  H01L2224/214

Abstract: A package structure and a manufacturing method are provided. The package structure includes a first circuit layer, a first dielectric layer, an electrical device and a first conductive structure. The first circuit layer includes a first alignment portion. The first dielectric layer covers the first circuit layer. The electrical device is disposed on the first dielectric layer, and includes an electrical contact aligning with the first alignment portion. The first conductive structure extends through the first alignment portion, and electrically connects the electrical contact and the first alignment portion.

公开(公告)号：US11664301B2

公开(公告)日：2023-05-30

申请号：US17205967

申请日：2021-03-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49827

Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface of the substrate. The substrate has a through opening extending between the first surface of the substrate and the second surface of the substrate. The semiconductor device package also includes a conductive pad in the through opening and approximal to the second surface of the substrate. The conductive pad has a first surface and a second surface opposite to the first surface of the conductive pad. The semiconductor device package also includes a conductive pillar in contact with the first surface of the conductive pad. The second surface of the conductive pad protrudes from the second surface of the substrate. A method of manufacturing a semiconductor device package is also disclosed.

公开(公告)号：US11610834B2

公开(公告)日：2023-03-21

申请号：US16655178

申请日：2019-10-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Bernd Karl Appelt

IPC: H01L23/495 ,  H01L23/00

Abstract: A leadframe includes a first conductive layer, a plurality of conductive pillars and a first package body. The first conductive layer has a first surface and a second surface opposite to the first surface. The plurality of conductive pillars are disposed on the first surface of the first conductive layer. The first package body is disposed on the first surface of the first conductive layer and covers the conductive pillars. The conductive pillars and the first conductive layer are integratedly formed.

公开(公告)号：US10755994B2

公开(公告)日：2020-08-25

申请号：US16173974

申请日：2018-10-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

公开(公告)号：US09659853B2

公开(公告)日：2017-05-23

申请号：US14696355

申请日：2015-04-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： You-Lung Yen ,  Chih-Cheng Lee ,  Yuan-Chang Su

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68345 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/73204

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.