公开(公告)号：US20110194352A1

公开(公告)日：2011-08-11

申请号：US12702948

申请日：2010-02-09

申请人： Yijie Zhao ,  Akira Goda

发明人： Yijie Zhao ,  Akira Goda

IPC分类号： G11C16/04 ,  G11C7/00

CPC分类号： G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454

摘要： Memory devices and programming methods for memories are disclosed, such as those adapted to program a memory using an increasing channel voltage for a first portion of programming, and an increasing but reduced channel voltage for a second portion of programming.

摘要翻译： 公开了用于存储器的存储器件和编程方法，诸如适于使用用于编程的第一部分的增加的沟道电压对存储器进行编程的那些，以及用于第二部分编程的增加但是减小的沟道电压。

公开(公告)号：US20110188312A1

公开(公告)日：2011-08-04

申请号：US13082965

申请日：2011-04-08

申请人： Akira Goda ,  Andrei Mihnea

发明人： Akira Goda ,  Andrei Mihnea

IPC分类号： G11C16/04 ,  G11C16/28

CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

摘要翻译： 本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。 一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

公开(公告)号：US20110164455A1

公开(公告)日：2011-07-07

申请号：US13049464

申请日：2011-03-16

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/3468

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses.

摘要翻译： 本公开的实施例提供用于编程存储器单元的方法，设备，模块和系统。 一种方法包括确定用于将阵列的一组存储器单元放置在擦除状态中的擦除脉冲的量，以及至少部分地基于确定的擦除量来调整与编程存储器单元组相关联的至少一个操作参数 脉冲。

公开(公告)号：US07883964B2

公开(公告)日：2011-02-08

申请号：US12181978

申请日：2008-07-29

申请人： Akira Goda ,  Hiroyuki Nitta

发明人： Akira Goda ,  Hiroyuki Nitta

IPC分类号： H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/0416 ,  G11C16/0483 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526

摘要： A nonvolatile semiconductor memory includes: a device region and a device isolating region, which have a pattern with a striped form that extends in a first direction, and are alternately and sequentially disposed at a first pitch in a second direction that is perpendicular to the first direction; and a contact made of a first conductive material, which is connected to the device region and disposed at the first pitch in the second direction. On a cross section of the second direction, the bottom width of the contact is longer than the top width of the contact, and the bottom width is longer than the width of the device region.

摘要翻译： 非易失性半导体存储器包括：器件区域和器件隔离区域，其具有沿第一方向延伸的条纹形式的图案，并且在垂直于第一方向的第二方向上以第一间距交替地并且顺序地设置 方向; 以及由第一导电材料制成的接触件，其连接到器件区域并沿第二方向以第一间距设置。 在第二方向的横截面上，触点的底部宽度比触点的顶部宽度长，并且底部宽度比器件区域的宽度长。

公开(公告)号：US20100091544A1

公开(公告)日：2010-04-15

申请号：US12637163

申请日：2009-12-14

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C5/06 ,  G11C7/10

CPC分类号： G11C7/02 ,  G11C7/1036 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： A memory device includes a first bit line coupled to a first source/drain region of a first multiplexer gate, a second bit line coupled to a first source/drain region of a second multiplexer gate, and a sensing device having an input coupled to a second source/drain region of the first multiplexer gate and a second source/drain region of the second multiplexer gate. The input of the sensing device is formed at a vertical level that is different than a vertical level at which at least one of the first and second bit lines is formed.

摘要翻译： 存储器件包括耦合到第一多路复用器门的第一源极/漏极区域的第一位线，耦合到第二多路复用器栅极的第一源极/漏极区域的第二位线以及耦合到第二多路复用器栅极的输入的感测器件 第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第二源极/漏极区域。 感测装置的输入形成在与形成第一和第二位线中的至少一个的垂直电平不同的垂直电平处。

公开(公告)号：US07656709B2

公开(公告)日：2010-02-02

申请号：US11800002

申请日：2007-05-03

申请人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

发明人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

摘要翻译： 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US07633786B2

公开(公告)日：2009-12-15

申请号：US11405762

申请日：2006-04-18

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C5/06

CPC分类号： G11C7/02 ,  G11C7/1036 ,  H01L27/105 ,  H01L27/11517 ,  H01L27/11526

摘要： Methods and apparatus are provided. A memory device includes a first bit line selectively coupled to an input of a sensing device through a first multiplexer gate, and a second bit line selectively coupled to the input of the sensing device through a second multiplexer gate. The first bit line is formed at a first vertical layer and is coupled to a first source/drain region of the first multiplexer gate. The input of the sensing device is formed at a second vertical layer different than the first vertical layer and is coupled to a second source/drain region of the first multiplexer gate and a first source/drain region of the second multiplexer gate. The second bit line is formed at the first vertical layer and is coupled to a second source/drain region of the second multiplexer gate.

摘要翻译： 提供了方法和装置。 存储器件包括通过第一多路复用器门选择性地耦合到感测器件的输入的第一位线，以及通过第二复用器门选择性地耦合到感测器件的输入的第二位线。 第一位线形成在第一垂直层并且耦合到第一多路复用器门的第一源/漏区。 感测装置的输入形成在不同于第一垂直层的第二垂直层上，并且耦合到第一多路复用器栅极的第二源极/漏极区域和第二多路复用器栅极的第一源极/漏极区域。 第二位线形成在第一垂直层处，并且耦合到第二多路复用器门的第二源极/漏极区域。

公开(公告)号：US07372113B2

公开(公告)日：2008-05-13

申请号：US10880508

申请日：2004-07-01

申请人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

发明人： Masayuki Tanaka ,  Yoshio Ozawa ,  Shigehiko Saida ,  Akira Goda ,  Mitsuhiro Noguchi ,  Yuichiro Mitani ,  Yoshitaka Tsunashima

IPC分类号： H01L21/314

CPC分类号： H01L21/022 ,  H01L21/0217 ,  H01L21/28176 ,  H01L21/28202 ,  H01L21/28247 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/76838 ,  H01L21/76897 ,  H01L29/513 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/792

摘要： Disclosed is a semiconductor device comprising a semiconductor substrate, a gate electrode, a first insulating film formed between the semiconductor substrate and the gate electrode, and a second insulating film formed along a top surface or a side surface of the gate electrode and including a lower silicon nitride film containing nitrogen, silicon and hydrogen and an upper silicon nitride film formed on the lower silicon nitride film and containing nitrogen, silicon and hydrogen, and wherein a composition ratio N/Si of nitrogen (N) to silicon (Si) in the lower silicon nitride film is higher than that in the upper silicon nitride film.

摘要翻译： 公开了一种半导体器件，包括半导体衬底，栅电极，形成在半导体衬底和栅电极之间的第一绝缘膜，以及沿着栅电极的顶表面或侧表面形成的第二绝缘膜， 包含氮，硅和氢的氮化硅膜和形成在下部氮化硅膜上并含有氮，硅和氢的上部氮化硅膜，并且其中氮（N）与硅（Si）的组成比N / Si在 下氮化硅膜比上述氮化硅膜高。

公开(公告)号：US07326993B2

公开(公告)日：2008-02-05

申请号：US10890132

申请日：2004-07-14

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/788 ,  H01L23/522

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

公开(公告)号：US20080008006A1

公开(公告)日：2008-01-10

申请号：US11900443

申请日：2007-09-12

申请人： Akira Goda ,  Seiichi Aritome ,  Todd Marquart

发明人： Akira Goda ,  Seiichi Aritome ,  Todd Marquart

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/3427

摘要： A NAND architecture non-volatile memory device and programming process is described that programs the various cells of strings of non-volatile memory cells by the application of differing word line pass voltages (Vpass) to the unselected word lines of the memory cell string or array during an programming cycle. In one embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized depending on the placement of the memory cell in the NAND memory cell string. In another embodiment of the present invention, the differing word line pass voltages (Vpass) are utilized to compensate for faster and slower programming word lines/memory cells.

摘要翻译： 描述了NAND​​架构非易失性存储器件和编程过程，其通过将不同字线通过电压（Vpass）应用到存储器单元串或阵列的未选择字线来对非易失性存储器单元串的各个单元进行编程 在编程周期。 在本发明的一个实施例中，根据存储器单元在NAND存储器单元串中的位置，利用不同的字线通过电压（Vpass）。 在本发明的另一个实施例中，利用不同的字线通过电压（Vpass）来补偿更快和更慢的编程字线/存储器单元。