公开(公告)号：US20110200059A1

公开(公告)日：2011-08-18

申请号：US13126032

申请日：2008-10-30

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： H04L12/56

CPC分类号： H04L25/49 ,  G11C7/1006

摘要： In accordance with embodiments, a system includes a first component and a second component. The system also includes a communication interface between the first and second components. A communication packet transmitted from the first component to the second component comprises a bit inversion identifier.

摘要翻译： 根据实施例，系统包括第一部件和第二部件。 该系统还包括第一和第二组件之间的通信接口。 从第一分量发送到第二分量的通信分组包括位反转标识符。

公开(公告)号：US06608564B2

公开(公告)日：2003-08-19

申请号：US09770100

申请日：2001-01-25

申请人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

发明人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

IPC分类号： G08B2300

CPC分类号： G06F13/4081 ,  G06F13/409

摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

公开(公告)号：US6141708A

公开(公告)日：2000-10-31

申请号：US98015

申请日：1998-06-15

申请人： Siamak Tavallaei ,  Brian T. Purcell ,  Brian S. Hausauer

发明人： Siamak Tavallaei ,  Brian T. Purcell ,  Brian S. Hausauer

IPC分类号： G06F13/40 ,  G06F13/14

CPC分类号： G06F13/4027

摘要： A computer system with an Intelligent Input/Output architecture having a scheme for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, a first input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions. A masking module is provided for rendering at least a portion of the plurality of peripheral devices hidden from the host operating system and host processors. The masking module is configured upon system initialization and the contents of the module are used in blocking IDSEL signals associated with the portion of peripheral devices subordinated to an I/O processor.

摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏至少一部分外围设备的方案。 该计算机系统包括至少一个用于执行主机操作系统的主机处理器，主机处理器设置在主机总线上，第一输入/输出（I / O）总线，可操作地经主机到总线桥接到主机总线 以及可操作地连接到I / O总线以在I / O事务中传送数据的多个外围设备。 提供掩蔽模块，用于使从主机操作系统和主处理器隐藏的多个外围设备的至少一部分。 掩蔽模块在系统初始化时配置，并且模块的内容用于阻止与从属于I / O处理器的外围设备的部分相关联的IDSEL信号。

公开(公告)号：US6097619A

公开(公告)日：2000-08-01

申请号：US100919

申请日：1998-06-19

申请人： Kevin Nguyen ,  Binh Quang Nguyen ,  Siamak Tavallaei

发明人： Kevin Nguyen ,  Binh Quang Nguyen ,  Siamak Tavallaei

IPC分类号： G11C5/12 ,  G11C5/06

CPC分类号： G11C5/12

摘要： A memory storage system includes a motherboard, a first memory card, and second memory card. The motherboard has a first and second electrical connector. The first memory card has a plurality of electrical connections coupled to the first electrical connector on the motherboard. The first memory card is adapted to receive a plurality of data signals over the first electrical connector and store the data signals in a first preselected pattern. A second memory card has a plurality of electrical connections coupled to the second electrical connector on the motherboard. The second memory card is adapted to receive a plurality of data signals over the second electrical connector and store the data signals in a second preselected pattern, different from the first preselected pattern.

摘要翻译： 存储器存储系统包括主板，第一存储卡和第二存储卡。 主板具有第一和第二电连接器。 第一存储卡具有耦合到主板上的第一电连接器的多个电连接。 第一存储卡适于在第一电连接器上接收多个数据信号，并以第一预选图案存储数据信号。 第二存储卡具有耦合到母板上的第二电连接器的多个电连接。 第二存储卡适于在第二电连接器上接收多个数据信号，并以与第一预选图案不同的第二预选图案存储数据信号。

公开(公告)号：US6055647A

公开(公告)日：2000-04-25

申请号：US912184

申请日：1997-08-15

申请人： John S. Lacombe ,  Jose A. Santin ,  Siamak Tavallaei

发明人： John S. Lacombe ,  Jose A. Santin ,  Siamak Tavallaei

IPC分类号： G06F11/20 ,  G06F11/30 ,  G06F11/00

CPC分类号： G06F11/3051 ,  G06F11/2015 ,  G06F11/3058

摘要： Apparatus, and an associated method, for determining the level of power supply redundancy in a modular computer system. Determination of the level of power supply redundancy is made dynamically, during on-line operation of the computer system. Reconfiguration of the computer system, such as to increase the load which must be powered by modular power supply components, or removal or addition of power supply components to form portions of the computer system cause initiation of a new determination of the level of power supply redundancy. Indications of inadequate levels of power supply redundancy are provided to a user of the computer system so that corrective action can be taken.

摘要翻译： 用于确定模块化计算机系统中的电源冗余度的装置和相关联的方法。 在计算机系统的在线操作期间，动态地确定电源冗余度。 计算机系统的重新配置，例如增加必须由模块化电源组件供电的负载，或移除或添加电源组件以形成计算机系统的一部分，引起新的电源冗余级别的确定 。 向计算机系统的用户提供不充分电源冗余的指示，从而可以采取纠正措施。

公开(公告)号：US6038633A

公开(公告)日：2000-03-14

申请号：US912096

申请日：1997-08-15

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G06F13/24 ,  G06F13/14

CPC分类号： G06F13/24

摘要： A system and an associated method which provides a dual interrupt mechanism to designate the occurrence and termination of an event. In a computer system employing redundant components, upon removal of a defective redundant unit within the computer system, a first interrupt is generated to signal the absence of the unit. Polling or other system monitoring of the status of the absent unit is masked or disabled, thereby eliminating unnecessary polling for the missing unit. Upon replacement of the unit, a second interrupt alerts the computer system of the event termination and cancels the polling mask.

摘要翻译： 一种提供双重中断机制来指定事件的发生和终止的系统和相关联的方法。 在采用冗余组件的计算机系统中，在移除计算机系统中的有缺陷的冗余单元之后，产生第一个中断以表示该单元的不存在。 对缺席单元状态的轮询或其他系统监视被屏蔽或禁用，从而消除对丢失单元的不必要的轮询。 更换单元后，第二个中断将告警计算机系统的事件终止，并取消轮询掩码。

公开(公告)号：US5948090A

公开(公告)日：1999-09-07

申请号：US92681

申请日：1998-06-05

申请人： David Heinrich ,  Robert Olson ,  Siamak Tavallaei

发明人： David Heinrich ,  Robert Olson ,  Siamak Tavallaei

IPC分类号： G06F1/24 ,  G06F13/40 ,  G06F13/24

CPC分类号： G06F13/4081 ,  G06F1/24

摘要： An apparatus controls a signal that indicates to a plug-in component board that it is to be connected to a 64-bit data path in a computer system. The apparatus comprises a timing circuit for receiving a reset signal and providing first and second complementary logical signals in response thereto. A selection switch receives the first and second logical signals as well as a control signal and outputs a third signal as determined by the logical level of the reset signal. A method involves generating first and second complementary signals from a reset signal, selecting between the first complementary signal and a control signal, and outputting a third signal, the logical value of the third signal being determined by the logical value of at least one of the reset signal and the control signal.

摘要翻译： 装置控制向插件组件板指示其要连接到计算机系统中的64位数据路径的信号。 该装置包括一个定时电路，用于接收复位信号并响应于此提供第一和第二互补逻辑信号。 选择开关接收第一和第二逻辑信号以及控制信号，并输出由复位信号的逻辑电平确定的第三信号。 一种方法包括从复位信号产生第一和第二互补信号，在第一互补信号和控制信号之间进行选择，并输出第三信号，第三信号的逻辑值由至少一个 复位信号和控制信号。

公开(公告)号：US08020053B2

公开(公告)日：2011-09-13

申请号：US12260917

申请日：2008-10-29

申请人： Lidia Warnes ,  Siamak Tavallaei

发明人： Lidia Warnes ,  Siamak Tavallaei

IPC分类号： G11C29/00

CPC分类号： G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

摘要： A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported.

摘要翻译： 公开了一种测试在线和备用存储器的方法。 这样的存储器当前可能在某些地址存储使用中的数据。 在发生预选条件时开始测试。 确定地址范围至少排除当前存储功能数据的地址。 地址范围受到测试模式的影响，并报告地址范围中的错误。

公开(公告)号：US20100107010A1

公开(公告)日：2010-04-29

申请号：US12260917

申请日：2008-10-29

申请人： Lidia Warnes ,  Siamak Tavallaei

发明人： Lidia Warnes ,  Siamak Tavallaei

IPC分类号： G06F11/26

CPC分类号： G11C29/52 ,  G11C2029/0407 ,  G11C2029/0409

摘要： A method of testing on-line and spare memory is disclosed. Such memory may currently store in-use data at some addresses. The testing is initiated upon an occurrence of a pre-selected condition. An address range is determined that excludes at least the addresses currently storing functional data. The address range is subjected to a test pattern, and errors in the address range are reported.

摘要翻译： 公开了一种测试在线和备用存储器的方法。 这样的存储器当前可能在某些地址存储使用中的数据。 在发生预选条件时开始测试。 确定地址范围至少排除当前存储功能数据的地址。 地址范围受到测试模式的影响，并报告地址范围中的错误。

公开(公告)号：US07116241B2

公开(公告)日：2006-10-03

申请号：US10437571

申请日：2003-05-14

申请人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

发明人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

IPC分类号： G08B23/00

CPC分类号： G06F13/4081 ,  G06F13/409

摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.