公开(公告)号：US5948090A

公开(公告)日：1999-09-07

申请号：US92681

申请日：1998-06-05

申请人： David Heinrich ,  Robert Olson ,  Siamak Tavallaei

发明人： David Heinrich ,  Robert Olson ,  Siamak Tavallaei

IPC分类号： G06F1/24 ,  G06F13/40 ,  G06F13/24

CPC分类号： G06F13/4081 ,  G06F1/24

摘要： An apparatus controls a signal that indicates to a plug-in component board that it is to be connected to a 64-bit data path in a computer system. The apparatus comprises a timing circuit for receiving a reset signal and providing first and second complementary logical signals in response thereto. A selection switch receives the first and second logical signals as well as a control signal and outputs a third signal as determined by the logical level of the reset signal. A method involves generating first and second complementary signals from a reset signal, selecting between the first complementary signal and a control signal, and outputting a third signal, the logical value of the third signal being determined by the logical value of at least one of the reset signal and the control signal.

摘要翻译： 装置控制向插件组件板指示其要连接到计算机系统中的64位数据路径的信号。 该装置包括一个定时电路，用于接收复位信号并响应于此提供第一和第二互补逻辑信号。 选择开关接收第一和第二逻辑信号以及控制信号，并输出由复位信号的逻辑电平确定的第三信号。 一种方法包括从复位信号产生第一和第二互补信号，在第一互补信号和控制信号之间进行选择，并输出第三信号，第三信号的逻辑值由至少一个 复位信号和控制信号。

公开(公告)号：US20110225353A1

公开(公告)日：2011-09-15

申请号：US13126141

申请日：2008-10-30

申请人： Robert C Elliott ,  Joseph E. Foster ,  Siamak Tavallaei

发明人： Robert C Elliott ,  Joseph E. Foster ,  Siamak Tavallaei

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0804 ,  G06F2212/2022

摘要： In at least some embodiments, a computing system includes a processor and a communication bus external to the processor. The computing system also includes a Redundant Array of Independent Disks (RAID) write cache sub-assembly coupled to the communication bus, the RAID write cache sub-assembly having non-volatile memory.

摘要翻译： 在至少一些实施例中，计算系统包括处理器和处理器外部的通信总线。 计算系统还包括耦合到通信总线的独立磁盘冗余阵列（RAID）写高速缓存子组件，该RAID写高速缓存子组件具有非易失性存储器。

公开(公告)号：US6134579A

公开(公告)日：2000-10-17

申请号：US911842

申请日：1997-08-15

申请人： Siamak Tavallaei ,  Jeffrey S. Autor

发明人： Siamak Tavallaei ,  Jeffrey S. Autor

IPC分类号： G06F15/177 ,  G06F9/46 ,  G06F13/362 ,  G06F9/00

CPC分类号： G06F9/52 ,  G06F2209/503

摘要： A computer system utilizing multiple processes includes a semaphore for controlling exclusive access of a single process to a selected resource. The semaphore is implemented in the system input/output and controlled, at least in part, by an application specific integrated circuit (ASIC). When a process is attempting to acquire an I/O resource, a read is sent to the semaphore. If the resource is available the semaphore will have a first value, and the semaphore will return that first value to the process indicating that the process has acquired the resource. The ASIC will then change the semaphore value to a second value. If the resource is not available the semaphore will have the second value, and the semaphore will return the second value to the process indicating that the resource is not available.

摘要翻译： 利用多个进程的计算机系统包括用于控制单个进程对所选资源的独占访问的信号量。 信号量在系统输入/输出中实现，至少部分地由专用集成电路（ASIC）控制。 当进程尝试获取I / O资源时，会将读取信息发送到信号量。 如果资源可用，则信号量将具有第一个值，并且信号量将返回该指示进程已获取资源的进程的第一个值。 然后，ASIC将信号量值更改为第二个值。 如果资源不可用，则信号量将具有第二个值，并且信号量将将第二个值返回给指示资源不可用的进程。

公开(公告)号：US20140211544A1

公开(公告)日：2014-07-31

申请号：US14342431

申请日：2011-09-02

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C5/04 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0073

摘要： Apparatus to store data and methods to read memory cells are disclosed. A disclosed example method involves, during a read cycle of a memory cell, applying a current across the memory cell to read a content of the memory cell. During a subsequent read cycle of the memory cell, a subsequent current is applied across the memory cell in the opposite direction to read the content of the memory cell.

摘要翻译： 公开了存储用于读取存储器单元的数据和方法的装置。 所公开的示例性方法涉及在存储器单元的读取周期期间，跨过存储器单元施加电流以读取存储器单元的内容。 在存储器单元的随后的读取周期期间，沿相反方向跨越存储器单元施加随后的电流以读取存储器单元的内容。

公开(公告)号：US07447818B2

公开(公告)日：2008-11-04

申请号：US10716144

申请日：2003-11-18

申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

IPC分类号： G06F15/16 ,  G06F3/00

CPC分类号： G06F11/2294

摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

公开(公告)号：US06792490B2

公开(公告)日：2004-09-14

申请号：US09991058

申请日：2001-11-16

申请人： Siamak Tavallaei

发明人： Siamak Tavallaei

IPC分类号： G06F1314

CPC分类号： G06F13/4027

摘要： A computer system with an Intelligent Input/Output architecture having a dynamic device blocking mechanism for hiding at least a portion of peripheral devices. The computer system comprises at least one host processor for executing a host operating system, the host processor disposed on a host bus, an input/output (I/O) bus operably coupled to the host bus via a host-to-bus bridge, and a plurality of peripheral devices operably connected to the I/O bus for transferring data in I/O transactions controlled by an IOP resource. A plurality of I/O bus signals are supplied to the device blocking module for determining which bus master owns the I/O bus in order to initiate a bus cycle. If the bus cycle is about to be commenced on behalf of the host processor and its OS, an enable signal associated with the selected peripheral device is negated until the cycle is completed. If, on the other hand, the bus cycle is initiated by the IOP, the enable signal is asserted for the duration of the transaction, which signal, otherwise, remains in a negated state.

摘要翻译： 具有智能输入/输出架构的计算机系统具有用于隐藏外围设备的至少一部分的动态设备阻塞机制。 计算机系统包括用于执行主机操作系统的主机处理器，设置在主机总线上的主机处理器，经由主机到总线桥接器可操作地耦合到主机总线的输入/输出（I / O）总线， 以及可操作地连接到I / O总线的用于在由IOP资源控制的I / O事务中传送数据的多个外围设备。 多个I / O总线信号被提供给器件阻塞模块，用于确定哪个总线主机拥有I / O总线以便启动总线周期。 如果总线周期即将代表主处理器及其OS开始，则与选定的外围设备相关联的使能信号被否定，直到该周期完成。 另一方面，如果由IOP启动总线周期，则在交易持续时间内使能使能信号，否则，该信号保持在否定状态。

公开(公告)号：US06747563B2

公开(公告)日：2004-06-08

申请号：US10437567

申请日：2003-05-14

申请人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

发明人： Christian H. Post ,  George D. Megason ,  Brett D. Roscoe ,  Paul Santeler ,  John M. MacLaren ,  John E. Larson ,  Jeffery Galloway ,  Siamak Tavallaei ,  Tim W. Majni ,  Robert Allan Lester ,  Anisha Anand ,  Eric Rose

IPC分类号： G08B2300

CPC分类号： G06F13/4081 ,  G06F13/409

摘要： A processor-based device having a plurality of memory cartridges secured within a chassis by a lever system. The processor-based device comprises an indication system to indicate memory system operating conditions. Each memory cartridge has a protective assembly to protect memory elements within the memory cartridge when the memory cartridge is removed from the processor-based device. The processor-based device is operable such that at least one memory cartridge may be removed from the processor-based device without affecting operation of the processor-based device.

摘要翻译： 一种基于处理器的设备，其具有通过杠杆系统固定在底盘内的多个存储器盒。 基于处理器的设备包括用于指示存储器系统操作条件的指示系统。 当从基于处理器的设备移除存储器盒时，每个存储器盒具有保护组件以保护存储器盒内的存储器元件。 基于处理器的设备是可操作的，使得可以从基于处理器的设备移除至少一个存储盒，而不影响基于处理器的设备的操作。

公开(公告)号：US06742066B2

公开(公告)日：2004-05-25

申请号：US10108106

申请日：2002-03-27

申请人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

发明人： Theodore F. Emerson ,  Siamak Tavallaei ,  John V. Butler

IPC分类号： G06F1516

CPC分类号： G06F11/2294

摘要： A computer system, such as a server disposed in an enterprise, accessible from a remote terminal for remote management applications. The computer system includes a remote console functionality assist logic structure for effectuating the sending and receiving of signals from the remote terminal. The remote console functionality assist logic structure is controlled by a dedicated processor that receives interrupts therefrom in response to a remote management application. The processor can also control one or more peripheral devices provided in the computer system, wherein the controlled peripheral device or devices are disposed up-stream or down-stream from the processor.

摘要翻译： 计算机系统，例如设置在企业中的服务器，可从远程终端访问用于远程管理应用。 计算机系统包括用于实现从远程终端发送和接收信号的远程控制台功能辅助逻辑结构。 远程控制台功能辅助逻辑结构由专用处理器控制，专用处理器响应于远程管理应用从其接收中断。 处理器还可以控制在计算机系统中提供的一个或多个外围设备，其中受控的外围设备或设备从处理器的上游或下游设置。

公开(公告)号：US6098143A

公开(公告)日：2000-08-01

申请号：US105725

申请日：1998-06-25

申请人： Brian Humpherys ,  John Butler ,  Siamak Tavallaei ,  Theodore F. Emerson ,  Doron Chosnek

发明人： Brian Humpherys ,  John Butler ,  Siamak Tavallaei ,  Theodore F. Emerson ,  Doron Chosnek

IPC分类号： G06F15/16

CPC分类号： G06F13/24 ,  H04N21/226 ,  H04N21/24 ,  H04N21/241 ,  H04N21/25

摘要： A computer system includes a bus, remote console logic, a remote server management device, and an interrupt routing switch. The bus has a first interrupt line. The remote console logic has a second interrupt line and is coupled to the bus. The remote console logic is adapted to monitor video transactions present on the bus. The video transactions include video data. The remote console logic is further adapted to store the video data and provide an interrupt signal on the second interrupt line if the amount of stored video data reaches a predetermined threshold. The remote server management device is coupled to the bus and the first interrupt line. The interrupt routing switch is coupled to the first interrupt line and the second interrupt line and adapted to couple the second interrupt line to the first interrupt line. A method for capturing video transactions includes coupling a first interrupt line of a buffer to a shared interrupt line of a bus. Video transactions occurring on the bus are snooped. The video transactions include video data. At least a portion of the video data is stored in the buffer. An interrupt signal is generated on the first interrupt line when the amount of data in the buffer reaches a predetermined threshold. The interrupt signal is received on the shared interrupt line in a remote server management device having memory. At least a portion of the video data is stored in the memory in response to the interrupt signal.

摘要翻译： 计算机系统包括总线，远程控制台逻辑，远程服务器管理装置和中断路由交换机。 总线有一条第一条中断线。 远程控制台逻辑具有第二个中断线，并连接到总线。 远程控制台逻辑适用于监视总线上存在的视频事务。 视频交易包括视频数据。 远程控制台逻辑还适于存储视频数据，并且如果存储的视频数据量达到预定阈值，则在第二中断线上提供中断信号。 远程服务器管理设备耦合到总线和第一中断线。 中断路由开关耦合到第一中断线和第二中断线，并且适于将第二中断线耦合到第一中断线。 一种用于捕获视频事务的方法包括将缓冲器的第一中断线耦合到总线的共享中断线。 公交车上发生的视频事件被窥探。 视频交易包括视频数据。 视频数据的至少一部分被存储在缓冲器中。 当缓冲器中的数据量达到预定阈值时，在第一中断线上产生中断信号。 在具有存储器的远程服务器管理设备中的共享中断线路上接收到中断信号。 响应于中断信号，视频数据的至少一部分被存储在存储器中。

公开(公告)号：US5938751A

公开(公告)日：1999-08-17

申请号：US912092

申请日：1997-08-15

申请人： Siamak Tavallaei ,  Joseph P. Miller

发明人： Siamak Tavallaei ,  Joseph P. Miller

IPC分类号： G06F3/00 ,  G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4081

摘要： A bus ring-back and voltage over-shoot reduction apparatus with capability for rendering an expansion slot of a computer system hot-pluggable, wherein a logic gate controls a switching element so that when the element is turned on, the input and output (I/O) nodes of the element are in a low ohmic conductive relationship. One of the I/O nodes is coupled to an expansion card whereas the other node is coupled to a bus to which the expansion slot is connected. The apparatus operates as a level shifter wherein the output node voltage follows the input node voltage until pinch-off such that the output voltage remains substantially stable thereafter. The apparatus also isolates the expansion card from the bus when the system is running or during the powering up of the card.

摘要翻译： 一种具有能够呈现计算机系统的可插拔的计算机系统的扩展槽的总线环回和电压过拍还原装置，其中逻辑门控制开关元件，使得当元件被接通时，输入和输出（I / O）节点处于低欧姆导电关系。 I / O节点中的一个耦合到扩展卡，而另一个节点耦合到扩展槽连接到的总线。 该装置作为电平转换器工作，其中输出节点电压跟随输入节点电压直到夹断，使得输出电压在此之后保持基本稳定。 当系统运行或卡上电时，该设备还将扩展卡与总线隔离开来。