公开(公告)号：US06673662B2

公开(公告)日：2004-01-06

申请号：US10264135

申请日：2002-10-03

申请人： Ranbir Singh

发明人： Ranbir Singh

IPC分类号： H01L21338

CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/872 ,  Y10S438/931

摘要： Edge termination for a silicon carbide Schottky rectifier is provided by including a silicon carbide epitaxial region on a voltage blocking layer of the Schottky rectifier and adjacent a Schottky contact of the silicon carbide Schottky rectifier. The silicon carbide epitaxial layer may have a thickness and a doping level so as to provide a charge in the silicon carbide epitaxial region based on the surface doping of the blocking layer. The silicon carbide epitaxial region may form a non-ohmic contact with the Schottky contact. The silicon carbide epitaxial region may have a width of from about 1.5 to about 5 times the thickness of the blocking layer. Schottky rectifiers with such edge termination and methods of fabricating such edge termination and such rectifiers are also provided. Such methods may also advantageously improve the performance of the resulting devices and may simplify the fabrication process.

摘要翻译： 碳化硅肖特基整流器的边缘端接通过在肖特基整流器的电压阻挡层上包括碳化硅外延区并且与碳化硅肖特基整流器的肖特基接触相邻来提供。 碳化硅外延层可以具有厚度和掺杂水平，以便基于阻挡层的表面掺杂在碳化硅外延区域中提供电荷。 碳化硅外延区可以形成与肖特基接触的非欧姆接触。 碳化硅外延区域的宽度可以为阻挡层厚度的约1.5至约5倍。 还提供了具有这种边缘终端的肖特基整流器和制造这种边缘终端的方法以及这种整流器。 这样的方法还可以有利地改善所得到的器件的性能，并且可以简化制造过程。

公开(公告)号：US06509230B1

公开(公告)日：2003-01-21

申请号：US09597286

申请日：2000-06-20

申请人： Kumar Pradip Roy ,  Ranbir Singh

发明人： Kumar Pradip Roy ,  Ranbir Singh

IPC分类号： H01L218247

CPC分类号： H01L21/28202 ,  C30B29/06 ,  C30B33/005 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02304 ,  H01L21/02312 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/518

摘要： A memory cell of a non-volatile memory includes a tunnel oxide layer having graded portions with greatly reduced stress on a silicon substrate. The method of making the tunnel oxide preferably includes growing a first oxide portion by upwardly ramping the silicon substrate to a first temperature lower than a glass transition temperature, and exposing the silicon substrate to an oxidizing ambient at the first temperature and for a first time period. Also, the method includes growing a second oxide portion between the first oxide portion and the silicon substrate by exposing the silicon substrate to an oxidizing ambient at a second temperature higher than the glass transition temperature for a second time period. The second oxide portion may have a thickness in a range of about 2 to 50% of a total thickness of the graded, grown, tunnel oxide layer. The step of upwardly ramping preferably includes upwardly ramping the temperature at a relatively high ramping rate to reduce any oxide formed during the upward ramping.

摘要翻译： 非易失性存储器的存储单元包括具有在硅衬底上具有大大降低的应力的分级部分的隧道氧化物层。 制造隧道氧化物的方法优选包括通过将硅衬底向上倾斜到低于玻璃化转变温度的第一温度来生长第一氧化物部分，并且在第一温度和第一时间段将硅衬底暴露于氧化环境 。 此外，该方法包括通过在高于玻璃化转变温度的第二温度下将硅衬底暴露于氧化环境第二时间段，在第一氧化物部分和硅衬底之间生长第二氧化物部分。 第二氧化物部分可以具有在梯度生长的隧道氧化物层的总厚度的约2至50％的范围内的厚度。 向上倾斜的步骤优选地包括以相对高的斜坡速率向上倾斜温度以减少在向上斜坡期间形成的任何氧化物。

公开(公告)号：US06383879B1

公开(公告)日：2002-05-07

申请号：US09572060

申请日：2000-05-17

申请人： Isik C. Kizilyalli ,  Ranbir Singh ,  Lori Stirling

发明人： Isik C. Kizilyalli ,  Ranbir Singh ,  Lori Stirling

IPC分类号： H01L21336

CPC分类号： H01L21/823842 ,  H01L21/28079 ,  H01L29/4958

摘要： The present invention provides a semiconductor device located on a semiconductor substrate having opposite types of first and second transistors formed thereon. The device preferably includes a first gate electrode that includes a first metal gate electrode material having a work function compatible with the first transistor, and a second gate electrode that includes a second metal gate electrode material having a work function compatible with the second transistor and the first metal gate electrode material is also located over the second metal gate electrode material, which forms a gate stack.

公开(公告)号：US06324095B1

公开(公告)日：2001-11-27

申请号：US09567521

申请日：2000-05-09

申请人： Richard J. McPartland ,  Ranbir Singh

发明人： Richard J. McPartland ,  Ranbir Singh

IPC分类号： G11C1604

CPC分类号： H01L27/115 ,  G11C16/0408 ,  G11C16/0416 ,  G11C2216/10

摘要： The present invention provides memory circuit including a control input, a switch, and a voltage transfer structure including a linear capacitor that electrically couples the control input to the switch.

摘要翻译： 本发明提供了包括控制输入，开关和电压传输结构的存储电路，该结构包括将控制输入电耦合到开关的线性电容器。

公开(公告)号：US06121633A

公开(公告)日：2000-09-19

申请号：US82554

申请日：1998-05-21

申请人： Ranbir Singh ,  John W. Palmour

发明人： Ranbir Singh ,  John W. Palmour

IPC分类号： H01L21/331 ,  H01L29/12 ,  H01L29/24 ,  H01L29/73 ,  H01L29/78 ,  H01L31/0312

CPC分类号： H01L29/1608 ,  H01L29/73 ,  H01L29/7302

摘要： A MOS bipolar transistor is provide which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer a p-type base layer. Preferably the base layer is formed by epitaxial growth and formed as a mesa. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also included are means for converting electron current flowing between the source and the drain into hole current for injection into the p-type base layer. Means for reducing field crowding associated with an insulating layer of said nMOSFET may also be provided.

摘要翻译： 提供了一种MOS双极晶体管，其包括形成在大块单晶n型碳化硅衬底上并具有n型漂移层和p型基极层的碳化硅npn双极晶体管。 优选地，基底层通过外延生长形成并形成为台面。 在npn双极晶体管附近形成碳化硅nMOSFET，使得施加到nMOSFET的栅极的电压使npn双极晶体管进入导通状态。 nMOSFET具有形成的源极和漏极，以在双极晶体管处于导通状态时向npn双极晶体管提供基极电流。 还包括用于将源极和漏极之间流动的电子电流转换成用于注入p型基极层的空穴电流的装置。 也可以提供用于减少与所述nMOSFET的绝缘层相关的场拥挤的手段。

公开(公告)号：US5969378A

公开(公告)日：1999-10-19

申请号：US891221

申请日：1997-07-10

申请人： Ranbir Singh

发明人： Ranbir Singh

IPC分类号： H01L29/24 ,  H01L29/73 ,  H01L31/0312

CPC分类号： H01L29/73 ,  H01L29/1608 ,  H01L29/7302

摘要： A MOS bipolar transistor is provided which includes a silicon carbide npn bipolar transistor formed on a bulk single crystal n-type silicon carbide substrate and having an n-type drift layer and p-type base layer. A silicon carbide nMOSFET is formed adjacent the npn bipolar transistor such that a voltage applied to the gate of the nMOSFET causes the npn bipolar transistor to enter a conductive state. The nMOSFET has a source and a drain formed so as to provide base current to the npn bipolar transistor when the bipolar transistor is in a conductive state. Also provide are means for converting electrons flowing between the source and the drain into holes for injection into the p-type base layer. Unit cells and methods of forming such devices are also provided.

摘要翻译： 提供了一种MOS双极晶体管，其包括形成在大块单晶n型碳化硅衬底上并具有n型漂移层和p型基极层的碳化硅npn双极晶体管。 在npn双极晶体管附近形成碳化硅nMOSFET，使得施加到nMOSFET的栅极的电压使npn双极晶体管进入导通状态。 nMOSFET具有形成的源极和漏极，以在双极晶体管处于导通状态时向npn双极晶体管提供基极电流。 还提供将在源极和漏极之间流动的电子转换成用于注入到p型基极层的孔的装置。 还提供了单元电池和形成这种器件的方法。

公开(公告)号：US07982286B2

公开(公告)日：2011-07-19

申请号：US11427494

申请日：2006-06-29

申请人： Nace Rossi ,  Ranbir Singh

发明人： Nace Rossi ,  Ranbir Singh

IPC分类号： H01L27/08

CPC分类号： H01L21/76838 ,  H01L21/32051 ,  H01L23/5227 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This method includes providing a semiconductor substrate and depositing a metal layer over the semiconductor substrate that has an overall thickness of about 1 micron or greater. The metal layer is formed by depositing a first portion of the thickness of the metal layer, which has a compressive or tensile stress associated therewith over the semiconductor substrate. A stress-compensating layer is deposited over the first portion, such that the stress-compensating layer imparts a stress to the first portion that is opposite to the compressive or tensile stress associated with the first portion. A second portion of the thickness of the metal layer is then deposited over the stress-compensating layer.

摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方法包括提供半导体衬底并在半导体衬底上沉积总厚度为约1微米或更大的金属层。 通过在半导体衬底上沉积具有与其相关的压缩或拉伸应力的金属层的厚度的第一部分来形成金属层。 应力补偿层沉积在第一部分上，使得应力补偿层向与第一部分相关联的压缩或拉伸应力相反的第一部分赋予应力。 然后将金属层的厚度的第二部分沉积在应力补偿层上。

公开(公告)号：US07906407B2

公开(公告)日：2011-03-15

申请号：US11926469

申请日：2007-10-29

申请人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

发明人： Nace Rossi ,  Ranbir Singh ,  Arun K. Nanda

IPC分类号： H01L21/76

CPC分类号： H01L21/31116 ,  H01L21/76205 ,  H01L21/76232

摘要： A shallow trench isolation structure having a negative taper angle and a method for forming same. A silicon nitride layer formed over a semiconductor substrate is etched according to a plasma etch process to form a first opening therein having sidewalls that present a negative taper angle. The substrate is etched to form a trench therein underlying the first opening. Silicon dioxide fills both the opening and the trench to form the shallow trench isolation structure, with the silicon dioxide in the opening exhibiting a negative taper angle to avoid formation of conductive stringers during subsequent process steps.

摘要翻译： 具有负锥角的浅沟槽隔离结构及其形成方法。 根据等离子体蚀刻工艺蚀刻形成在半导体衬底上的氮化硅层，以形成其中具有负锥角的侧壁的第一开口。 蚀刻衬底以在第一开口下方形成沟槽。 二氧化硅填充开口和沟槽以形成浅沟槽隔离结构，其中开口中的二氧化硅呈现负锥角，以避免在随后的工艺步骤期间形成导电条。

公开(公告)号：US07764541B2

公开(公告)日：2010-07-27

申请号：US10586176

申请日：2004-01-23

申请人： Ross Alan Kohler ,  Richard Joseph McPartland ,  Ranbir Singh

发明人： Ross Alan Kohler ,  Richard Joseph McPartland ,  Ranbir Singh

IPC分类号： G11C11/34

CPC分类号： G11C17/14 ,  H01L27/112

摘要： One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

摘要翻译： 公开了一次可编程存储器件，其使用热载流子诱导劣化来编程以改变一个或多个晶体管特性。 一次可编程存储器件由晶体管阵列组成。 阵列中的晶体管使用热载流子引起的一个或多个晶体管特性的改变（例如晶体管的饱和电流，阈值电压或两者的改变）来选择性地编程。 以与已知的热载流子晶体管老化原理相似的方式实现晶体管特性的变化。 所公开的一次可编程存储器件小，可在低电压和小电流下编程。

公开(公告)号：US20090127651A1

公开(公告)日：2009-05-21

申请号：US12356600

申请日：2009-01-21

申请人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun K. Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。