公开(公告)号：US07764541B2

公开(公告)日：2010-07-27

申请号：US10586176

申请日：2004-01-23

申请人： Ross Alan Kohler ,  Richard Joseph McPartland ,  Ranbir Singh

发明人： Ross Alan Kohler ,  Richard Joseph McPartland ,  Ranbir Singh

IPC分类号： G11C11/34

CPC分类号： G11C17/14 ,  H01L27/112

摘要： One time programmable memory devices are disclosed that are programmed using hot carrier induced degradation to alter one or more transistors characteristics. A one time programmable memory device is comprised of an array of transistors. Transistors in the array are selectively programmed using hot carrier induced changes in one or more transistor characteristics, such as changes to the saturation current, threshold voltage or both, of the transistors. The changes to the transistor characteristics are achieved in a similar manner to known hot carrier transistor aging principles. The disclosed one time programmable memory devices are small and programmable at low voltages and small current.

摘要翻译： 公开了一次可编程存储器件，其使用热载流子诱导劣化来编程以改变一个或多个晶体管特性。 一次可编程存储器件由晶体管阵列组成。 阵列中的晶体管使用热载流子引起的一个或多个晶体管特性的改变（例如晶体管的饱和电流，阈值电压或两者的改变）来选择性地编程。 以与已知的热载流子晶体管老化原理相似的方式实现晶体管特性的变化。 所公开的一次可编程存储器件小，可在低电压和小电流下编程。

公开(公告)号：US06512700B1

公开(公告)日：2003-01-28

申请号：US09956646

申请日：2001-09-20

申请人： Richard Joseph McPartland ,  Ranbir Singh

发明人： Richard Joseph McPartland ,  Ranbir Singh

IPC分类号： G11C1604

CPC分类号： H01L29/42336 ,  G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L29/7885

摘要： A non-volatile memory cell and associated cell array and memory device having reduced program disturb, improved retention of programmed information, and reduced power consumption are disclosed. The memory cell includes a control device coupled to a switch device via a common floating gate, with the control device and the switch device formed on a common substrate, and the switch device formed at least in part in a tub region on the substrate. The tub region has a contact region formed therein. The contact region is adapted for application of a bias voltage to the tub region during a programming operation of the memory cell so as to reduce a programming voltage required to program the memory cell. In an illustrative embodiment, a drain-to-substrate voltage required to program the memory cell is reduced from a conventional value of about 6.5 volts to a value of about 3.5 volts, thus alleviating program disturb problems that can result, e.g., when the drain-to-substrate voltage is applied to multiple columns of an array of cells that are programmed one row at a time. The memory cell is programmed by channel initiated secondary electron (CHISEL) injection of charge onto the floating gate. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.

摘要翻译： 公开了一种非易失性存储单元和相关联的单元阵列以及具有减少的程序干扰，改进的编程信息保留和降低的功耗的存储器件。 存储单元包括通过公共浮动栅极耦合到开关装置的控制装置，其中控制装置和开关装置形成在公共基板上，并且开关装置至少部分地形成在基板上的桶区域中。 桶区具有形成在其中的接触区域。 接触区域适于在存储单元的编程操作期间向桶区域施加偏置电压，以便减少编程存储单元所需的编程电压。 在说明性实施例中，对存储器单元编程所需的漏极到衬底的电压从约6.5伏特的常规值减小到约3.5伏特的值，从而减轻程序干扰问题，例如当漏极 对基板电压施加到一行一行编程的单元阵列的多列。 通过通道引发的二次电子（CHISEL）将电荷注入浮置栅极来对存储单元进行编程。 本发明特别适用于集成电路应用中的单聚焦闪存EEPROM嵌入式存储器件中的实现。

公开(公告)号：US06459615B1

公开(公告)日：2002-10-01

申请号：US09910980

申请日：2001-07-23

申请人： Richard Joseph McPartland ,  Ranbir Singh

发明人： Richard Joseph McPartland ,  Ranbir Singh

IPC分类号： G11C1604

CPC分类号： H01L27/115 ,  G11C16/0433 ,  G11C2216/10 ,  H01L27/11558

摘要： A non-volatile memory device is disclosed which includes an erase device that is shared among an array of memory cells. Each of the memory cells in the array includes a control device coupled to a switch device via a common floating gate. Each of at least a subset of the memory cells further includes a portion of the shared erase device, the portion of the shared erase device associated with a given one of the memory cells being coupled to the switch device of that cell via the floating gate of that cell. The shared erase device is utilizable in performing an erase operation for each of the memory cells associated therewith. Advantageously, the use of the shared erase device substantially reduces the circuit area requirements of the memory array. The invention is particularly well suited for implementation in single-poly flash EEPROM embedded memory devices in integrated circuit applications.

摘要翻译： 公开了一种非易失性存储器件，其包括在存储器单元阵列之间共享的擦除装置。 阵列中的每个存储器单元包括通过公共浮动栅极耦合到开关器件的控制器件。 存储器单元的至少一个子集中的每一个还包括共享擦除装置的一部分，与存储器单元中的给定一个存储器单元相关联的共享擦除装置的部分经由浮动栅极的浮动栅极耦合到该单元的开关装置 那个单元格。 共享擦除装置可用于对与其相关联的每个存储单元执行擦除操作。 有利地，共享擦除装置的使用大大减少了存储器阵列的电路面积要求。 本发明特别适用于集成电路应用中的单聚焦闪存EEPROM嵌入式存储器件中的实现。

公开(公告)号：US07982239B2

公开(公告)日：2011-07-19

申请号：US11808915

申请日：2007-06-13

申请人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

发明人： Ty R. McNutt ,  Eric J. Stewart ,  Rowland C. Clarke ,  Ranbir Singh ,  Stephen Van Campen ,  Marc E. Sherwin

IPC分类号： H01L29/47

CPC分类号： H01L27/098 ,  H01L21/8232 ,  H01L27/0727 ,  H01L27/095 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66909 ,  H01L29/7397 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8122 ,  H01L29/872

摘要： In an embodiment, a integrated semiconductor device includes a first Vertical Junction Field Effect Transistor (VJFET) having a source, and a gate disposed on each side of the first VJFET source, and a second VJFET transistor having a source, and a gate disposed on each side of the second VJFET source. At least one gate of the first VJFET is separated from at least one gate of the second VJFET by a channel. The integrated semiconductor device also includes a Junction Barrier Schottky (JBS) diode positioned between the first and second VJFETs. The JBS diode comprises a metal contact that forms a rectifying contact to the channel and a non-rectifying contact to at least one gate of the first and second VJFETs, and the metal contact is an anode of the JBS diode. A first electrical connection ties the gates of the first VJFET, the gates of the second VJFET, and the anode of the JBS diode to a common gate electrode and a second electrical connection ties the source of the first VJFET and the source of the second VJFET to a common source electrode.

摘要翻译： 在一个实施例中，集成半导体器件包括具有源极的第一垂直结型场效应晶体管（VJFET）和设置在第一VJFET源的每一侧上的栅极和具有源极的第二VJFET晶体管，栅极设置在 第二VJFET源的每一侧。 第一VJFET的至少一个栅极通过沟道与第二VJFET的至少一个栅极分离。 集成半导体器件还包括位于第一和第二VJFET之间的结栅势垒肖特基（JBS）二极管。 JBS二极管包括形成与沟道的整流接触的金属接触和与第一和第二VJFET的至少一个栅极的非整流接触，并且金属接触是JBS二极管的阳极。 第一电连接将第一VJFET的栅极，第二VJFET的栅极和JBS二极管的阳极连接到公共栅电极，并且第二电连接将第一VJFET的源极和第二VJFET的源极连接 到共同的源电极。

公开(公告)号：US07843030B2

公开(公告)日：2010-11-30

申请号：US11689524

申请日：2007-03-22

申请人： Ranbir Singh

发明人： Ranbir Singh

IPC分类号： H01L31/101

CPC分类号： H01L31/107 ,  H01L27/1446 ,  H01L31/1105

摘要： Here, we demonstrate new material/structures for the photodetectors, using semiconductor material. For example, we present the Tunable Avalanche Wide Base Transistor as a photodetector. Particularly, SiC, GaN, AlN, Si and Diamond materials are given as examples. The desired properties of an optimum photodetector is achieved. Different variations are discussed, both in terms of structure and material.

摘要翻译： 在这里，我们展示了使用半导体材料的光电探测器的新材料/结构。 例如，我们将可调谐雪崩宽基极晶体管作为光电检测器。 特别地，作为实例给出了SiC，GaN，AlN，Si和金刚石材料。 实现了最佳光电探测器所需的性能。 在结构和材料方面讨论了不同的变化。

公开(公告)号：US20090050977A1

公开(公告)日：2009-02-26

申请号：US12256677

申请日：2008-10-23

申请人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

发明人： Alan S. Chen ,  Mark Dyson ,  Nace M. Rossi ,  Ranbir Singh ,  Xiaojun Yuan

IPC分类号： H01L27/06

CPC分类号： H01L29/7378 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66242

摘要： The invention, in one aspect, provides a method of manufacturing a semiconductor device. This aspect includes forming gate electrodes in a non-bipolar transistor region of a semiconductor substrate, placing a polysilicon layer over the gate electrodes in the non-bipolar transistor region and over the semiconductor substrate within a bipolar transistor region. A protective layer is formed over the polysilicon layer. The protective layer has a weight percent of hydrogen that is less than about 9% and is selective to silicon germanium (SiGe), such that SiGe does not form on the protective layer. This aspect further includes forming emitters for bipolar transistors in the bipolar transistor region, including forming a SiGe layer under a portion of the polysilicon layer.

摘要翻译： 本发明在一个方面提供一种制造半导体器件的方法。 该方面包括在半导体衬底的非双极晶体管区域中形成栅电极，将多晶硅层放置在非双极晶体管区域中的栅电极之上，并在双极晶体管区域内的半导体衬底上。 在多晶硅层上形成保护层。 保护层具有小于约9％的氢的重量百分数，并且对硅锗（SiGe）是选择性的，使得SiGe不在保护层上形成。 该方面还包括在双极晶体管区域中形成用于双极晶体管的发射极，包括在多晶硅层的一部分下形成SiGe层。

公开(公告)号：US07427326B2

公开(公告)日：2008-09-23

申请号：US11560575

申请日：2006-11-16

申请人： Joseph J. Sumakeris ,  Ranbir Singh ,  Michael James Paisley ,  Stephan Georg Mueller ,  Hudson M. Hobgood ,  Calvin H. Carter, Jr. ,  Albert Augustus Burk, Jr.

发明人： Joseph J. Sumakeris ,  Ranbir Singh ,  Michael James Paisley ,  Stephan Georg Mueller ,  Hudson M. Hobgood ,  Calvin H. Carter, Jr. ,  Albert Augustus Burk, Jr.

IPC分类号： C30B25/12

CPC分类号： H01L29/1608 ,  C30B19/00 ,  C30B23/002 ,  C30B25/02 ,  C30B29/36 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/744 ,  H01L29/861

摘要： A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.

摘要翻译： 形成双极性器件的方法包括在衬底上形成至少一个单晶碳化硅的p型层和至少一个单晶碳化硅n型层。 在设备的正向操作下生长的堆叠故障与活动区域和设备的其余部分之间的至少一个接口分离。 形成双极器件的方法包括将至少一个外延层生长至大于该层中的少数载流子扩散长度的厚度。 该方法还增加了漂移区周围的外延层的掺杂浓度，以减少其中的少数载流子寿命。

公开(公告)号：US20070190803A1

公开(公告)日：2007-08-16

申请号：US11738050

申请日：2007-04-20

申请人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

发明人： Ranbir Singh ,  Sen Sidhartha ,  Nace Rossi

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02063 ,  H01L21/02052 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76831 ,  Y10S438/963

摘要： The present invention provides an interconnect that can be employed in an integrated circuit. The interconnect includes a metal line located over a substrate, a dielectric layer located over the metal line, and an interconnect located in the dielectric layer, including a landed portion located over the metal line and an unlanded portion located along at least a portion of a lateral edge of the metal line. The unlanded portion is at least partially filled with a polymer, and the landed portion is substantially filled with a conductive material. A method for manufacturing the interconnect is also provided.

摘要翻译： 本发明提供了可以用于集成电路中的互连。 互连包括位于衬底上的金属线，位于金属线上方的电介质层和位于电介质层中的互连，其包括位于金属线上的着陆部分和位于金属线的至少一部分上的非上限部分 金属线的侧边。 至少部分地用聚合物填充未上敷的部分，并且所述着陆部分基本上填充有导电材料。 还提供了用于制造互连的方法。

公开(公告)号：US20070152294A1

公开(公告)日：2007-07-05

申请号：US11321206

申请日：2005-12-29

申请人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L29/00 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/3145 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/76232

摘要： In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

摘要翻译： 在半导体衬底中，具有设置在沟槽填充材料的空隙中的介电材料的浅沟槽隔离结构和用于形成浅沟槽隔离结构的方法。 在电介质材料形成在沟槽中之后，可以在湿式清洁工艺期间形成空隙。 在衬底上和空隙中形成保形氮化硅层。 在移除氮化硅层之后，空隙至少部分地被氮化硅材料填充。

公开(公告)号：US20060068562A1

公开(公告)日：2006-03-30

申请号：US10953632

申请日：2004-09-29

申请人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

发明人： Arun Nanda ,  Nace Rossi ,  Ranbir Singh

IPC分类号： H01L21/76

CPC分类号： H01L21/76232 ,  H01L21/823878

摘要： The present invention provides a trench isolation structure, a method for manufacturing a trench isolation structure, and a method for manufacturing an integrated circuit including the trench isolation structure. In one aspect, the method includes forming a hardmask over a substrate, etching a trench in the substrate through the hardmask, forming a liner in the trench, depositing an interfacial layer over the liner within the trench and over the hardmask and filling the trench with a dielectric material.

摘要翻译： 本发明提供一种沟槽隔离结构，一种用于制造沟槽隔离结构的方法，以及一种用于制造包括沟槽隔离结构的集成电路的方法。 在一个方面，该方法包括在衬底上形成硬掩模，通过硬掩模蚀刻衬底中的沟槽，在沟槽中形成衬垫，在沟槽内并在硬掩模上方的衬垫上沉积界面层，并在硬掩模上填充沟槽，并用 介电材料。