公开(公告)号：US07026867B2

公开(公告)日：2006-04-11

申请号：US10879606

申请日：2004-06-28

申请人： Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

发明人： Robert J. Drost ,  Ronald Ho ,  Ivan E. Sutherland

IPC分类号： H03F1/02

CPC分类号： H03F3/45977 ,  H03F3/08

摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.

摘要翻译： 本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。 在输入端编程一个直流电压。 在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值 接收放大器的电压。 然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。 由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。

公开(公告)号：US08242811B2

公开(公告)日：2012-08-14

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US20110248750A1

公开(公告)日：2011-10-13

申请号：US12758189

申请日：2010-04-12

申请人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

发明人： Jae-sun Seo ,  Ronald Ho ,  Robert J. Drost ,  Robert D. Hopkins

IPC分类号： H03K3/00

CPC分类号： G06F13/4072 ,  G06F2213/0038 ,  H03K3/3565 ,  Y02D10/14 ,  Y02D10/151

摘要： Some embodiments of the present invention provide techniques and systems for high-bandwidth on-chip communication. During operation, the system receives an input voltage signal which is to be transmitted over a wire in a chip. The system then generates one or more modified voltage signals from the input voltage signal. Next, the system drives each of the voltage signals (i.e., the input voltage signal and the one or more modified voltage signals) through a respective capacitor. The system then combines the output signals from the capacitors to obtain a combined voltage signal. Next, the system transmits the combined voltage signal over the wire. The transmitted signals can then be received by a hysteresis receiver which is coupled to the wire through a coupling capacitor.

摘要翻译： 本发明的一些实施例提供了用于高带宽片上通信的技术和系统。 在操作期间，系统接收将通过芯片中的导线传输的输入电压信号。 然后，该系统从输入电压信号产生一个或多个修改的电压信号。 接下来，系统通过相应的电容器驱动每个电压信号（即，输入电压信号和一个或多个修改的电压信号）。 然后，系统组合来自电容器的输出信号以获得组合电压信号。 接下来，系统通过电线传输组合的电压信号。 所传送的信号然后可以由滞后接收器接收，该滞后接收器通过耦合电容耦合到导线。

公开(公告)号：US08035977B1

公开(公告)日：2011-10-11

申请号：US11098724

申请日：2005-04-04

申请人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

发明人： Ronald Ho ,  Robert J. Drost ,  Robert Hopkins

IPC分类号： H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC分类号： G06F1/189

摘要： One embodiment of the present invention provides a system that reduces power consumption by using capacitive coupling to perform a majority detection operation. The system starts by driving a plurality of signals onto a plurality of driven wires. The signals are then fed from each driven wire through a corresponding coupling capacitor to a single majority detection wire. Next, the system feeds signal on the majority detection wire and a bias voltage to a differential receiver. The output of the differential receiver switches if the signal on the majority-detection wire switches relative to the bias voltage. The system then uses the output of the differential receiver to optimize the signals from the plurality of driven wires for transmission across a long signal route. Optimizing the transmission of signals reduces the power consumed by the computer system.

摘要翻译： 本发明的一个实施例提供一种通过使用电容耦合来执行多数检测操作来降低功耗的系统。 系统通过将多个信号驱动到多个从动线上开始。 然后，这些信号从每个从动导线通过相应的耦合电容器馈送到单个多数检测线。 接下来，系统将多数检测线上的信号馈送到差分接收器的偏置电压。 如果多数检测线上的信号相对于偏置电压切换，差分接收器的输出将切换。 然后，系统使用差分接收器的输出来优化来自多条驱动线的信号，以便在长信号路径上传输。 优化信号传输减少了计算机系统消耗的功耗。

公开(公告)号：US08024623B2

公开(公告)日：2011-09-20

申请号：US12263713

申请日：2008-11-03

申请人： Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham ,  Robert J. Drost

发明人： Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham ,  Robert J. Drost

IPC分类号： G11B5/00

CPC分类号： H04B5/0075 ,  H01L25/065 ,  H01L2924/0002 ,  H04B17/318 ,  H04L1/0009 ,  Y10T29/49133 ,  H01L2924/00

摘要： In a proximity communication system, transmit elements on one chip are aligned with receive elements on a second chip juxtaposed with the first chip. However, if the elements are misaligned, either statically or dynamically, the coupling between chips is degraded. The misalignment may be compensated by controllably degrading performance of the system. For example, the transmit signal strength may be increased. The bit period or the time period for biasing each bit may be increased, thereby decreasing the bandwidth. Multiple coupling elements, such as capacitors, may be ganged together, thereby decreasing the number of channels. The granularity of symbols, such as images, may be increased by decreasing the number of bits per symbol.

摘要翻译： 在接近通信系统中，一个芯片上的发射元件与与第一芯片并置的第二芯片上的接收元件对齐。 然而，如果元件是静态的或动态的，则芯片之间的耦合会降低。 可以通过可控地降低系统的性能来补偿未对准。 例如，可以增加发射信号强度。 可以增加用于偏置每个位的位周期或时间段，从而降低带宽。 诸如电容器的多个耦合元件可以组合在一起，从而减少通道数量。 可以通过减少每个符号的比特数来增加诸如图像的符号的粒度。

公开(公告)号：US07840136B1

公开(公告)日：2010-11-23

申请号：US11728844

申请日：2007-03-26

申请人： John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Ronald Ho ,  Robert J. Drost

发明人： John E. Cunningham ,  Ashok V. Krishnamoorthy ,  Ronald Ho ,  Robert J. Drost

IPC分类号： H04J14/00 ,  G02B6/26

CPC分类号： H04Q11/0005 ,  H04Q3/66 ,  H04Q2011/0039 ,  H04Q2011/005 ,  H04Q2011/0052

摘要： Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an electrical control path. Note that the electrical control path is configured to use proximity communication to communicate the flow-control information. Furthermore, the switching elements are configured to selectively couple the input ports to the output ports via optical signal paths based on the flow-control information.

摘要翻译： 描述开关的实施例。 该开关包括被配置为接收被配置为输出信号的信号（其包括数据）和输出端口的输入端口。 此外，开关包括开关元件和流量控制机构，其被配置为经由电控制路径向开关元件提供与数据相关联的流量控制信息。 注意，电气控制路径被配置为使用邻近通信来传达流量控制信息。 此外，开关元件被配置为基于流量控制信息经由光信号路径选择性地将输入端口耦合到输出端口。

公开(公告)号：US07817880B1

公开(公告)日：2010-10-19

申请号：US11728845

申请日：2007-03-26

申请人： Robert J. Drost ,  Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

发明人： Robert J. Drost ,  Ronald Ho ,  Ashok V. Krishnamoorthy ,  John E. Cunningham

IPC分类号： G02B6/10 ,  G02B6/12

CPC分类号： G02B6/43 ,  G02B6/35 ,  H04B10/803

摘要： Embodiments of a system are described. This system includes an array of single-chip modules (CMs), which includes a first CM and a second CM which are coupled to each other. A given CM, which can be either the first CM or the second CM, includes a semiconductor die that is configured to communicate data signals with other CMs by capacitively coupled proximity communication and optical proximity communication using proximity connectors. These proximity connectors are proximate to a surface of the semiconductor die, and the semiconductor die includes an optical signal path configured to communicate on-chip optical signals.

摘要翻译： 描述系统的实施例。 该系统包括单芯片模块（CM）的阵列，其包括彼此耦合的第一CM和第二CM。 可以是第一CM或第二CM的给定CM包括被配置为通过电容耦合的邻近通信和使用接近连接器的光学邻近通信与其他CM通信数据信号的半导体管芯。 这些接近连接器靠近半导体管芯的表面，并且半导体管芯包括被配置为传送片上光信号的光信号通路。

公开(公告)号：US20090193295A1

公开(公告)日：2009-07-30

申请号：US12352488

申请日：2009-01-12

申请人： Robert J. Drost ,  Ronald Ho ,  Justin M. Schauer

发明人： Robert J. Drost ,  Ronald Ho ,  Justin M. Schauer

IPC分类号： G06F11/07

CPC分类号： G01R31/31932 ,  G01R31/31922 ,  G01R31/31937 ,  H01L23/48 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10T29/49133 ,  H01L2924/00

摘要： A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.

摘要翻译： 一种通过在一个芯片上的发送器与另一个芯片上的接收器之间的数据链路上施加电压的电压裕度来测试接近通信系统的方法，该电容耦合电路通过在相应的两个并置电容器焊盘上形成的电容耦合电路 筹码 外加电压变化，监视接收器的输出以确定工作电压裕量。 接收器上的浮动输入可以通过将其通过高阻抗连接到可变的偏置电源电压而被连续地偏置。 当在静止数据周期期间将浮动输入周期性地刷新到刷新电压时，刷新电压在连续刷新周期之间变化。 可变测试电压在高阻抗状态时可以应用于发射机输出，并测量接收机的输出。

公开(公告)号：US07129712B1

公开(公告)日：2006-10-31

申请号：US11256733

申请日：2005-10-24

申请人： Robert J. Drost ,  R. David Hopkins ,  Ronald Ho

发明人： Robert J. Drost ,  R. David Hopkins ,  Ronald Ho

IPC分类号： G01R27/26

CPC分类号： G01R27/2605

摘要： An electrical circuit for determining a capacitance is described. The electrical circuit includes a first device, a rectifying circuit and a feedback circuit. The first device has a first terminal and a second terminal. The first device has a first unknown capacitance and the first terminal may be configured to receive a time-varying voltage signal. The rectifying circuit has an input terminal, an output terminal and a feedback terminal. The input terminal may be coupled to the second terminal and the output terminal may be configured for coupling to an output electrical circuit. The feedback circuit may selectively couple the output terminal to the input terminal using the feedback terminal such that the output terminal and the input terminal are substantially at a common voltage.

摘要翻译： 描述用于确定电容的电路。 电路包括第一装置，整流电路和反馈电路。 第一装置具有第一端子和第二端子。 第一器件具有第一未知电容，并且第一端子可以被配置为接收时变电压信号。 整流电路具有输入端子，输出端子和反馈端子。 输入端可以耦合到第二端子，并且输出端子可以被配置为耦合到输出电路。 反馈电路可以使用反馈端选择性地将输出端耦合到输入端，使得输出端和输入端基本上处于公共电压。

公开(公告)号：US07694203B2

公开(公告)日：2010-04-06

申请号：US11773020

申请日：2007-07-03

申请人： Frankie Y. Liu ,  Ronald Ho ,  Robert J. Drost

发明人： Frankie Y. Liu ,  Ronald Ho ,  Robert J. Drost

IPC分类号： G01R31/28

CPC分类号： G01R31/31705 ,  G01R19/0053 ,  G01R31/2884

摘要： Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.

摘要翻译： 描述包括调试电路的集成电路的实施例。 该调试电路被配置为通过对与异步电路相关联的异步信号执行模拟测量来测试异步电路，并且包括被配置为基于一个或多个异步信号门控调试电路的触发模块。 该触发模块具有连续的操作模式和单次操作模式。 调试电路内的定时模块具有超过预定值的定时范围，并且被配置为提供对应于第一时基的信号或对应于第二时基的信号。 此外，调试电路内的控制逻辑被配置为选择作为第一时基或第二时基的调试电路的操作模式和给定时基。