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    Register caching techniques for thread switches
    21.
    发明授权
    Register caching techniques for thread switches 有权

    公开(公告)号：US09817664B2

    公开(公告)日：2017-11-14

    申请号：US14625956

    申请日：2015-02-19

    Applicant: Apple Inc.

    Inventor： Shachar Ron ,  Bernard J. Semeria

    IPC: G06F9/30

    CPC classification number: G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

    Abstract: Techniques are disclosed relating to register caching techniques for thread switches. In one embodiment, an apparatus includes a register file and caching circuitry. In this embodiment, the register file includes a plurality of registers and the caching circuitry is configured to store information that indicates threads that correspond to data stored in respective ones of the plurality of registers. In this embodiment, the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers. In some embodiments, the disclosed techniques may reduce context switch latency, reduce pressure on a data cache, and/or allow smaller slices of thread execution, for example.

    REGISTER CACHING TECHNIQUES FOR THREAD SWITCHES
    22.
    发明申请
    REGISTER CACHING TECHNIQUES FOR THREAD SWITCHES 有权
    用于螺纹开关的寄存器高速缓存技术

    公开(公告)号：US20160246728A1

    公开(公告)日：2016-08-25

    申请号：US14625956

    申请日：2015-02-19

    Applicant: Apple Inc.

    Inventor： Shachar Ron ,  Bernard J. Semeria

    IPC: G06F12/08 ,  G06F9/30

    CPC classification number: G06F9/30098 ,  G06F9/30123 ,  G06F9/3851

    Abstract: Techniques are disclosed relating to register caching techniques for thread switches. In one embodiment, an apparatus includes a register file and caching circuitry. In this embodiment, the register file includes a plurality of registers and the caching circuitry is configured to store information that indicates threads that correspond to data stored in respective ones of the plurality of registers. In this embodiment, the apparatus is configured to store, at a point in time at which a first register of the plurality of registers includes first valid data corresponding to a first thread, second valid data corresponding to a second thread in a second register of the plurality of registers. In some embodiments, the disclosed techniques may reduce context switch latency, reduce pressure on a data cache, and/or allow smaller slices of thread execution, for example.

    Abstract translation: 公开了关于线程开关的寄存器缓存技术的技术。 在一个实施例中，装置包括寄存器文件和高速缓存电路。 在该实施例中，寄存器文件包括多个寄存器，并且高速缓存电路被配置为存储指示对应于存储在多个寄存器的相应数据中的数据的线程的信息。 在本实施例中，该装置被配置为在多个寄存器中的第一寄存器包括与第一线程相对应的第一有效数据的时间点存储对应于第一线程的第二寄存器中的第二线程的第二有效数据 多个寄存器。 在一些实施例中，例如，所公开的技术可以减少上下文切换等待时间，减少数据高速缓存上的压力和/或允许更小的线程执行。

    Memory error tracking and logging
    23.
    发明授权
    Memory error tracking and logging 有权

    公开(公告)号：US12253913B2

    公开(公告)日：2025-03-18

    申请号：US18438802

    申请日：2024-02-12

    Applicant: Apple Inc.

    Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

    IPC: G06F11/10 ,  G06F11/07

    Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

    Unified Addressable Memory
    27.
    发明申请
    Unified Addressable Memory 审中-公开

    公开(公告)号：US20200257829A1

    公开(公告)日：2020-08-13

    申请号：US16859634

    申请日：2020-04-27

    Applicant: Apple Inc.

    Inventor： Manu Gulati ,  Joseph Sokol, Jr. ,  Jeffrey R. Wilcox ,  Bernard J. Semeria ,  Michael J. Smith

    IPC: G06F21/72 ,  H04L9/08 ,  G06F21/78 ,  G06F12/14 ,  G06F12/1027 ,  G06F12/02

    Abstract: In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

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