公开(公告)号：US12243575B2

公开(公告)日：2025-03-04

申请号：US18515649

申请日：2023-11-21

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Farid Nemati

IPC: G11C11/402 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/02 ,  G11C11/406 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L27/02

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

公开(公告)号：US20190286519A1

公开(公告)日：2019-09-19

申请号：US16405362

申请日：2019-05-07

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Sukalpa Biswas ,  Jeffrey R. Wilcox ,  Farid Nemati

IPC: G06F11/10 ,  G11C29/52

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

公开(公告)号：US12253913B2

公开(公告)日：2025-03-18

申请号：US18438802

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

IPC: G06F11/10 ,  G06F11/07

Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

公开(公告)号：US20240161804A1

公开(公告)日：2024-05-16

申请号：US18515649

申请日：2023-11-21

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Farid Nemati

IPC: G11C11/402 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/02 ,  G11C11/406 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: G11C11/4023 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/02 ,  G11C11/40607 ,  H01L24/00 ,  H01L25/0652 ,  H01L25/105 ,  H01L25/0657 ,  H01L27/0203 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

公开(公告)号：US11934265B2

公开(公告)日：2024-03-19

申请号：US17804950

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Derek R. Kumar ,  Bernard J. Semeria ,  James Vash ,  Era K. Nangia ,  Gregory S. Mathews

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/106

Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

公开(公告)号：US10318377B2

公开(公告)日：2019-06-11

申请号：US16029829

申请日：2018-07-09

Applicant: Apple Inc.

Inventor： Manu Gulati ,  Sukalpa Biswas ,  Jeffrey R. Wilcox ,  Farid Nemati

IPC: G06F11/10 ,  G11C29/52 ,  G06F12/1072 ,  G06F12/121 ,  G06F12/06 ,  G06F12/126 ,  G11C29/04 ,  G11C29/44 ,  G11C29/00 ,  G06F12/12

Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

公开(公告)号：US20250157520A1

公开(公告)日：2025-05-15

申请号：US19022153

申请日：2025-01-15

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Farid Nemati

IPC: G11C11/402 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/02 ,  G11C11/406 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H10D89/00

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.

公开(公告)号：US12248369B2

公开(公告)日：2025-03-11

申请号：US18323178

申请日：2023-05-24

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

Abstract: Techniques are disclosed relating to improving memory reliability. In some embodiments, memory circuitry includes memory cells configured to store data, interface circuitry, and on-die error correcting code (ECC) circuitry. The ECC circuitry may check read data from the memory cells for errors and correct detected correctable errors to generate corrected data. The memory circuitry may provide read data to a requesting circuit via the interface circuitry, including one or more sets of corrected data from the on-die ECC circuitry. The memory circuitry may provide a decoding status flag (DSF) via the interface circuitry, including to: set the DSF to a first value in response to no error being detected for a given set of provided read data, set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data, and set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry.

公开(公告)号：US20230251930A1

公开(公告)日：2023-08-10

申请号：US17804932

申请日：2022-06-01

Applicant: Apple Inc.

Inventor： Farid Nemati ,  Steven R. Hutsell ,  Gregory S. Mathews ,  Yi Chun Chen ,  Kevin C. Wong ,  Kalpana Bansal

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1064 ,  G06F11/106 ,  G06F11/076 ,  G06F11/0772

Abstract: Techniques are disclosed relating to improving memory reliability, e.g., in the context of memory circuits with limited reliability features. In some embodiments, memory controller circuitry is configured to communicate with memory circuitry via an interface that supports link error detection. The memory controller circuitry may, based on a corruption indicator, transmit a data and parity combination for the first data block that causes the memory circuitry to detect an uncorrectable write interface error. Subsequent reads of the location may therefore cause an uncorrectable error indication. This may advantageously allow the memory controller circuitry to propagate a corruption indicator as an uncorrectable error in the memory circuit, without requiring additional tracking of the indicator by the memory circuit or memory controller, in some embodiments.

公开(公告)号：US20220415379A1

公开(公告)日：2022-12-29

申请号：US17895433

申请日：2022-08-25

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Farid Nemati

IPC: G11C11/402 ,  G11C5/06 ,  H01L23/00 ,  G11C5/04 ,  H01L25/10 ,  H01L25/065 ,  G11C5/02 ,  G11C7/02 ,  G11C11/406

Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g., an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.