公开(公告)号：US20160307621A1

公开(公告)日：2016-10-20

申请号：US15133400

申请日：2016-04-20

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/419 ,  H03K19/0185 ,  H03K3/356

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US20160179169A1

公开(公告)日：2016-06-23

申请号：US15049236

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

Abstract translation: 在一个实施例中，系统可以包括多个处理器和配置成在各个操作点之间切换处理器的自动功率状态控制器（APSC）。 操作点可以由编程到APSC中的数据描述，并且APSC可以包括可编程的寄存器，其具有从所描述的操作点中识别处理器的目标操作点的目标操作点请求。 描述操作点的数据还可以包括在操作点处可能同时活动的处理器的数量是否受限制的指示。 基于指示和有效处理器的数量，APSC可以以减小的操作点覆盖所请求的操作点。 在一些实施例中，数字功率估计器（DPE）可以监视处理器的操作，并且可以在检测到高功耗时调节处理器。

公开(公告)号：US09304573B2

公开(公告)日：2016-04-05

申请号：US13924164

申请日：2013-06-21

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.

Abstract translation: 在一个实施例中，系统可以包括多个处理器和配置成在各个操作点之间切换处理器的自动功率状态控制器（APSC）。 操作点可以由编程到APSC中的数据描述，并且APSC可以包括可编程的寄存器，其具有从所描述的操作点中识别处理器的目标操作点的目标操作点请求。 描述操作点的数据还可以包括在操作点处可能同时活动的处理器的数量是否受限制的指示。 基于指示和有效处理器的数量，APSC可以以减小的操作点覆盖所请求的操作点。 在一些实施例中，数字功率估计器（DPE）可以监视处理器的操作，并且可以在检测到高功耗时调节处理器。

公开(公告)号：US08848463B2

公开(公告)日：2014-09-30

申请号：US14095648

申请日：2013-12-03

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C7/00 ,  G11C11/417 ,  G11C11/419 ,  G11C8/08 ,  G11C7/12 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US08625368B2

公开(公告)日：2014-01-07

申请号：US13787894

申请日：2013-03-07

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C7/00

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract translation: 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20230122955A1

公开(公告)日：2023-04-20

申请号：US17821394

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US20190050043A1

公开(公告)日：2019-02-14

申请号：US16159821

申请日：2018-10-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US10101788B2

公开(公告)日：2018-10-16

申请号：US15433201

申请日：2017-02-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US20170236578A1

公开(公告)日：2017-08-17

申请号：US15583013

申请日：2017-05-01

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/419 ,  H03K19/0185

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US09703354B2

公开(公告)日：2017-07-11

申请号：US15049236

申请日：2016-02-22

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Daniel C. Murray ,  Wei-Han Lien

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/22

Abstract: In an embodiment, a system may include multiple processors and an automatic power state controller (APSC) configured to switch the processors between various operating points. The operating points may be described by data programmed into the APSC, and the APSC may include a register that is programmable with a target operating point request identifying a target operating point for the processors from among the described operating points. The data describing the operating points may also include an indication of whether or not the number of processors that may be concurrently active at the operating point is limited. Based on the indication and the number of active processors, the APSC may override the requested operating point with a reduced operating point. In some embodiments, a digital power estimator (DPE) may monitor operation of the processors and may throttle the processors when high power consumption is detected.