公开(公告)号：US20240429938A1

公开(公告)日：2024-12-26

申请号：US18755302

申请日：2024-06-26

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Karthik Ramani ,  Stephan Lachowsky ,  Justin A. Hensley ,  Davoud A. Jamshidi

IPC: H03M7/30 ,  H04N19/176 ,  H04N19/182

Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.

公开(公告)号：US11436784B2

公开(公告)日：2022-09-06

申请号：US17103406

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T15/00 ,  G06F9/48 ,  G06F9/50 ,  G06T1/20 ,  G06F16/22 ,  G06F30/31 ,  G06T17/10 ,  G16H40/67 ,  G06Q10/10 ,  G06Q50/04

Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

公开(公告)号：US11373360B2

公开(公告)日：2022-06-28

申请号：US17103317

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/50 ,  G06F16/22 ,  G06F30/31 ,  G06T17/10 ,  G16H40/67 ,  G06Q10/10 ,  G06Q50/04

Abstract: Disclosed techniques relate to grouping rays during traversal of a spatially-organized acceleration data structure (e.g., a bounding volume hierarchy) for ray intersection processing. The grouping may provide temporal locality for accesses to bounding region data. In some embodiments, ray intersect circuitry is configured to group rays based on the node of the data structure that they target next. The ray intersect circuitry may select one or more groups of rays for issuance each clock cycle, e.g., to bounding region test circuitry.

公开(公告)号：US11367242B2

公开(公告)日：2022-06-21

申请号：US17103433

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T15/00 ,  G06T17/00

Abstract: Disclosed techniques relate to ray intersection processing for ray tracing. In some embodiments, ray intersection circuitry traverses a spatially organized acceleration data structure and includes bounding region circuitry configured to test, in parallel, whether a ray intersects multiple different bounding regions indicated by a node of the data structure. Shader circuitry may execute a ray intersect instruction to invoke traversal by the ray intersect circuitry and the traversal may generate intersection results. The shader circuitry may shade intersected primitives based on the intersection results. Disclosed techniques that share processing between intersection circuitry and shader processors may improve performance, reduce power consumption, or both, relative to traditional techniques.

公开(公告)号：US20210336632A1

公开(公告)日：2021-10-28

申请号：US16855540

申请日：2020-04-22

Applicant: Apple Inc.

Inventor： Tyson J. Bergland ,  Karthik Ramani ,  Stephan Lachowsky ,  Justin A. Hensley ,  Davoud A. Jamshidi

IPC: H03M7/30 ,  H04N19/176 ,  H04N19/182

Abstract: Techniques are disclosed relating to compression of pixel data using different quantization for different regions of a block of pixels being compressed. In some embodiments, compression circuitry is configured to determine, for multiple components included in pixels of the block of pixels being compressed, respective smallest and greatest component values in respective regions of the block of pixels. The compression circuitry may determine, based on the determined smallest and greatest component values, to use a first number of bits to represent delta values relative to a base value for a first component in a first region and a second, different number of bits to represent delta values relative to a base value for a second component in the first region. The compression circuitry may then quantize delta values for the first and second components of pixels in the first region of the block of pixels using the determined first and second numbers of bits. In some embodiments, the compression circuitry determines whether to provide cross-component bit sharing within a region.

公开(公告)号：US20210312694A1

公开(公告)日：2021-10-07

申请号：US17352080

申请日：2021-06-18

Applicant: Apple Inc.

Inventor： Arthur Y Zhang ,  Ray L. Chang ,  Timothy R. Oriol ,  Ling Su ,  Gurjeet S. Saund ,  Guy Cote ,  Jim C. Chou ,  Hao Pan ,  Tobias Eble ,  Avi Bar-Zeev ,  Sheng Zhang ,  Justin A. Hensley ,  Geoffrey Stahl

IPC: G06T15/00 ,  H04W76/10 ,  G06F3/01 ,  G06T3/00 ,  G06T9/00

Abstract: A mixed reality system that includes a device and a base station that communicate via a wireless connection The device may include sensors that collect information about the user's environment and about the user. The information collected by the sensors may be transmitted to the base station via the wireless connection. The base station renders frames or slices based at least in part on the sensor information received from the device, encodes the frames or slices, and transmits the compressed frames or slices to the device for decoding and display. The base station may provide more computing power than conventional stand-alone systems, and the wireless connection does not tether the device to the base station as in conventional tethered systems. The system may implement methods and apparatus to maintain a target frame rate through the wireless link and to minimize latency in frame rendering, transmittal, and display.

公开(公告)号：US20210271606A1

公开(公告)日：2021-09-02

申请号：US16804128

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Justin A. Hensley ,  Karl D. Mann ,  Yoong Chert Foo ,  Terence M. Potter ,  Frank W. Liljeros ,  Ralph C. Taylor

IPC: G06F12/1018 ,  G06F12/084

Abstract: Techniques are disclosed relating to dynamically allocating and mapping private memory for requesting circuitry. Disclosed circuitry may receive a private address and translate the private address to a virtual address (which an MMU may then translate to physical address to actually access a storage element). In some embodiments, private memory allocation circuitry is configured to generate page table information and map private memory pages for requests if the page table information is not already setup. In various embodiments, this may advantageously allow dynamic private memory allocation, e.g., to efficiently allocate memory for graphics shaders with different types of workloads. Disclosed caching techniques for page table information may improve performance relative to traditional techniques. Further, disclosed embodiments may facilitate memory consolidation across a device such as a graphics processor.

公开(公告)号：US10445852B2

公开(公告)日：2019-10-15

申请号：US15388804

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Robert Kenney ,  Aaftab A. Munshi ,  Justin A. Hensley ,  Richard W. Schreyer

IPC: G06T1/20 ,  G06T1/60

Abstract: Techniques are disclosed relating to a hardware-supported flexible data structure for graphics processing. In some embodiments, dimensions of the data structure are configurable in an X direction, a Y direction, a number of samples per pixel, and an amount of data per sample. In some embodiments, these attributes are configurable using hardware registers. In some embodiments, the data structure is persistent across a tile being processed such that local memory context is accessible to both rendering threads of a render pass and mid-render compute threads.

公开(公告)号：US20180182058A1

公开(公告)日：2018-06-28

申请号：US15388804

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Robert Kenney ,  Aaftab A. Munshi ,  Justin A. Hensley ,  Richard W. Schreyer

IPC: G06T1/20 ,  G06T1/60

Abstract: Techniques are disclosed relating to a hardware-supported flexible data structure for graphics processing. In some embodiments, dimensions of the data structure are configurable in an X direction, a Y direction, a number of samples per pixel, and an amount of data per sample. In some embodiments, these attributes are configurable using hardware registers. In some embodiments, the data structure is persistent across a tile being processed such that local memory context is accessible to both rendering threads of a render pass and mid-render compute threads.

公开(公告)号：US20250111591A1

公开(公告)日：2025-04-03

申请号：US18978482

申请日：2024-12-12

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F16/22 ,  G06F30/31 ,  G06Q10/101 ,  G06Q50/04 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00 ,  G06T17/10 ,  G16H40/67

Abstract: Disclosed techniques relate to traversal techniques for ray tracing. In some embodiments, ray intersect circuitry receives a ray intersect request that indicates origin and direction information for a ray in a graphics scene. The ray intersect circuitry may traverse multiple nodes of a spatially organized acceleration data structure, wherein a given node of the multiple nodes indicates coordinates corresponding to a bounding region of the graphics scene. In response to detection that the ray intersects with a first bounding volume, the ray intersect circuitry stores a local parametric value for the ray that indicates a point at which the ray intersected the first bounding volume and may use the local parametric value as an origin value of the ray for one or more intersection tests between the ray and one or more child bounding volumes of the first bounding volume.