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60 条记录 (耗时 0.028 秒)

    MOS field effect transistor device with buried channel
    21.
    发明授权
    MOS field effect transistor device with buried channel 失效
    MOS场效应晶体管器件具有埋入通道

    公开(公告)号：US4916500A

    公开(公告)日：1990-04-10

    申请号：US78987

    申请日：1987-07-29

    申请人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

    发明人： Yoshiaki Yazawa ,  Atsuo Watanabe ,  Atsushi Hiraishi ,  Masataka Minami ,  Takahiro Nagano

    IPC分类号： H01L29/10 ,  H01L29/78 ,  H01L29/786 ,  H01L29/808

    CPC分类号： H01L29/78696 ,  H01L29/105 ,  H01L29/78 ,  H01L29/7838 ,  H01L29/808

    摘要： The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.

    摘要翻译： 本发明涉及一种包括第一导电类型或绝缘体的半导体衬底的半导体器件，包括设置在所述半导体衬底或所述绝缘体上的第二导电类型的杂质层的源极，包括第二导电类型或绝缘体的杂质层的漏极 设置在所述半导体衬底或所述绝缘体上的导电类型，形成在所述源极和所述漏极之间的第一导电类型的杂质层，经由绝缘膜形成在所述第一导电类型的所述杂质层上的栅极和 第二导电类型的杂质浓度低于所述源极和漏极的第二导电类型，所述第二导电类型的所述杂质层设置在所述源极，所述漏极和所述第一导电类型的所述杂质层之间，所述第一导电类型的所述半导体衬底 导电类型或所述绝缘体。

    Semiconductor device
    22.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4868626A

    公开(公告)日：1989-09-19

    申请号：US044202

    申请日：1987-04-30

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

    Semiconductor device
    23.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4672416A

    公开(公告)日：1987-06-09

    申请号：US843614

    申请日：1986-03-25

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/02

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

    AQUEOUS INK FOR INKJET RECORDING
    24.
    发明申请
    AQUEOUS INK FOR INKJET RECORDING 失效
    墨水记录墨水

    公开(公告)号：US20110263752A1

    公开(公告)日：2011-10-27

    申请号：US13131221

    申请日：2009-11-20

    申请人： Atsushi Hiraishi ,  Masayuki Narita ,  Takahiro Sato ,  Kyoichi Shirota ,  Yasuhiro Doi ,  Hiroyuki Yoshida ,  Yusuke Shimizu

    发明人： Atsushi Hiraishi ,  Masayuki Narita ,  Takahiro Sato ,  Kyoichi Shirota ,  Yasuhiro Doi ,  Hiroyuki Yoshida ,  Yusuke Shimizu

    IPC分类号： C09D11/10 ,  C09D139/00 ,  C09D179/02 ,  C08J3/22 ,  B01F3/12 ,  C09D133/10 ,  C08K5/3437

    CPC分类号： C09D11/322 ,  C09D11/326

    摘要： The present invention provides [1] a water dispersion for ink-jet printing containing chain-like particles each containing anionic organic pigment particles and a cationic polymer, wherein the ratio of organic pigment primary particles forming the chain-like particles to all the pigment primary particles contained in the water dispersion is 10% by number or more; [2] a water-based ink for ink-jet printing containing the water dispersion; [3] a method for producing a water dispersion for ink-jet printing as described above in [1]; and [4] a water-based ink for ink-jet printing containing a water dispersion produced through the method. The water dispersion and water-based ink for ink-jet printing of the present invention realize excellent optical density.

    摘要翻译： 本发明提供[1]一种喷墨印刷用水分散体，其含有各自含有阴离子性有机颜料粒子和阳离子性聚合物的链状粒子，其中，形成链状粒子的有机颜料一次粒子与全部颜料原料的比例 包含在水分散体中的颗粒为10个数量以上; [2]一种含有水分散体的喷墨印刷用水性油墨; [3]如上述[1]所述的喷墨打印用水分散体的制造方法， 和[4]一种用于喷墨印刷的水性油墨，其含有通过该方法制备的水分散体。 本发明的喷墨印刷用水分散体和水性油墨实现优异的光密度。

    Load reduced memory module
    25.
    发明申请
    Load reduced memory module 审中-公开
    减少内存模块

    公开(公告)号：US20100312956A1

    公开(公告)日：2010-12-09

    申请号：US12801325

    申请日：2010-06-03

    申请人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    发明人： Atsushi Hiraishi ,  Toshio Sugano ,  Fumiyuki Osanai ,  Masayuki Nakamura ,  Hiroki Fujisawa ,  Shunichi Saito

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G11C5/04 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A memory module includes a plurality of memory chips and a plurality of data register buffers mounted on the module substrate. At least two memory chips are allocated to each of the data register buffers. Each of the data register buffers includes M input/output terminals (M is a positive integer equal to or larger than 1) that are connected to the data connectors via a first data line and N input/output terminals (N is a positive integer equal to or larger than 2M) that are connected to corresponding memory chips via second and third data lines, so that the number of the second and third data lines is N/M times the number of the first data lines. According to the present invention, because the load capacities of the second and third data lines are reduced by a considerable amount, it is possible to realize a considerably high data transfer rate.

    摘要翻译： 存储器模块包括多个存储器芯片和安装在模块基板上的多个数据寄存器缓冲器。 至少两个存储器芯片被分配给每个数据寄存器缓冲器。 每个数据寄存器缓冲器包括通过第一数据线连接到数据连接器的M个输入/输出端子（M是等于或大于1的正整数）和N个输入/输出端子（N是正整数等于 大于2M），其经由第二和第三数据线连接到对应的存储器芯片，使得第二和第三数据线的数量是第一数据线的数量的N / M倍。 根据本发明，由于第二和第三数据线的负载容量减少了很多，所以可以实现相当高的数据传输速率。

    MEMORY MODULE, METHOD FOR USING SAME AND MEMORY SYSTEM
    28.
    发明申请
    MEMORY MODULE, METHOD FOR USING SAME AND MEMORY SYSTEM 有权
    存储器模块，使用它们的方法和存储器系统

    公开(公告)号：US20090303768A1

    公开(公告)日：2009-12-10

    申请号：US12477501

    申请日：2009-06-03

    申请人： Yoji NISHIO ,  Atsushi Hiraishi

    发明人： Yoji NISHIO ,  Atsushi Hiraishi

    IPC分类号： G11C5/02 ,  H03K17/16 ,  G11C5/06

    CPC分类号： G11C5/04 ,  G06F13/4072 ,  G06F13/4086 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73265 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    摘要： In a multi-rank memory module having a terminal resistance of a data input/output pad 13 and a terminal resistance control pad 14 that inputs a signal that controls on/off of the terminal resistance, a high-speed operation is enabled with the aid of an enclosed terminal resistance, even in cases where the number of ranks is greater than that of terminal resistance control terminals (ODT terminals) provided on the memory module. To this end, a terminal resistance control pad 14 of a memory chip 12, having a longer length of an interconnect between a data bus 19 on a module substrate 8 and a data input/output pad 13, is connected to a terminal resistance control interconnect 18 or 21 to control the on/off of the terminal resistance from the ODT terminal. A terminal resistance control pad on a memory chip 11, having a shorter length of an interconnect between the data bus 19 on the module substrate and the data input/output pad 13, is connected to a fixed potential 20 to turn on the terminal resistance.

    摘要翻译： 在具有数据输入/输出焊盘13的终端电阻的多级存储器模块和输入控制端子电阻的接通/断开的信号的端子电阻控制焊盘14的情况下，可以通过辅助来实现高速操作 即使在排列数大于设置在存储器模块上的端子电阻控制端子（ODT端子）的数量的情况下，也可以是封闭的端子电阻。 为此，在模块基板8上的数据总线19与数据输入/输出焊盘13之间具有较长互连长度的存储芯片12的端子电阻控制焊盘14连接到终端电阻控制互连 18或21以控制来自ODT端子的端子电阻的开/关。 在模块基板上的数据总线19与数据输入/输出焊盘13之间的互连的较短长度的存储芯片11上的端子电阻控制焊盘连接到固定电位20以接通端子电阻。

    Memory module
    29.
    发明申请
    Memory module 有权
    内存模块

    公开(公告)号：US20080123303A1

    公开(公告)日：2008-05-29

    申请号：US11987080

    申请日：2007-11-27

    申请人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    发明人： Toshio Sugano ,  Shunichi Saito ,  Atsushi Hiraishi

    IPC分类号： H05K7/00

    CPC分类号： H05K1/181 ,  G11C5/00 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/09627 ,  H05K2201/10159 ,  H05K2201/10545 ,  Y02P70/611

    摘要： A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.

    摘要翻译： 存储器模块包括经由模块基板设置在与存储器缓冲器相对的位置处的存储器芯片MC1，经由模块基板设置在与存储器缓冲器不相对的位置处的存储芯片MC 3和布置在存储器缓冲器 在与存储芯片MC3相对的位置经由模块基板。 连接到存储芯片MC 1的布线部分和连接到存储芯片MC 3和MC 11的布线部分分支的分支点位于从平面安装位置 的存储器缓冲器和存储芯片MC 3和MC 11的平面安装位置。因此，可以使布线部分的布线长度足够短。