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公开(公告)号：US20240120905A1
公开(公告)日：2024-04-11
申请号：US17963040
申请日：2022-10-10
发明人： Alireza Nilchi , Adesh Garg , Mohammad Elbadry , Ahmed Elkholy , Jun Cao
摘要： An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.
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22.发明公开公开(公告)号：US20240097692A1
公开(公告)日：2024-03-21
申请号：US18522698
申请日：2023-11-29
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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23.发明授权公开(公告)号：US11863198B2
公开(公告)日：2024-01-02
申请号：US17699678
申请日：2022-03-21
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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24.发明公开公开(公告)号：US20230299781A1
公开(公告)日：2023-09-21
申请号：US17699678
申请日：2022-03-21
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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25.发明公开公开(公告)号：US20230291411A1
公开(公告)日：2023-09-14
申请号：US17694225
申请日：2022-03-14
发明人： Yong Liu , Jun Cao , Delong Cui
IPC分类号： H03M1/10
CPC分类号： H03M1/1028
摘要： Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
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公开(公告)号：US20220404860A1
公开(公告)日：2022-12-22
申请号：US17841501
申请日：2022-06-15
发明人： Hongtao JIANG , Jun Cao , Afshin Momtaz , Armond Hairapetian , Kang Xiao
摘要： A system is provided that includes a first electronic device, multiple second electronic devices coupled to the first electronic device via respective interfaces, and a clock generator coupled to the second electronic devices and configured to generate and provide a clock signal to each of the second electronic devices for clocking operation of the second electronic devices. The clock signal is a gapped clock signal having at least one gap created by the clock generator removing one or more clock pulses based on a synchronization signal, and the second electronic devices are configured to synchronize data transmission between the second electronic devices and the first electronic device via the interfaces using the at least one gap in the gapped clock signal to align the data transmission.
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公开(公告)号：US10476516B1
公开(公告)日：2019-11-12
申请号：US16163446
申请日：2018-10-17
发明人： Kun Chuai , Afshin Momtaz , Jun Cao , Seong-Ho Lee , Burak Catli , Anand J. Vasani , Ali Nazemi
IPC分类号： H03M1/66 , H04B1/40 , H01L23/498
摘要： A pre-driver circuit includes a differential input circuit to receive a differential-input voltage. A latch circuit can latch voltage levels of output-voltage signals at a differential output port of the pre-driver circuit. A pair of capacitors couple the differential input circuit to the latch circuit. The pre-driver circuit can enable peaking of the output-voltage signals for high-speed operation of the pre-driver circuit and a digital-to-analog converter (DAC)-driver circuit coupled to the pre-driver circuit.
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公开(公告)号：US10277210B1
公开(公告)日：2019-04-30
申请号：US15794667
申请日：2017-10-26
发明人： Hyo Gyuem Rhew , Adesh Garg , Meisam Honarvar Nazari , Jiawen Zhang , Ali Nazemi , Jun Cao
摘要： A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.
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公开(公告)号：US12119835B2
公开(公告)日：2024-10-15
申请号：US17964031
申请日：2022-10-11
发明人： Ahmed Elkholy , Jun Cao , Adesh Garg
CPC分类号： H03M1/0626 , H03M1/066 , H03M1/0665 , H03M1/0673 , H03M1/66
摘要： A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
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公开(公告)号：US11916561B1
公开(公告)日：2024-02-27
申请号：US17582641
申请日：2022-01-24
发明人： Boyu Hu , Chang Liu , Guansheng Li , Haitao Wang , Delong Cui , Jun Cao
CPC分类号： H03M1/0607 , G06F1/06 , H03K5/13 , H03L7/087 , H03K2005/00052
摘要： An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.
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