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1.发明公开公开(公告)号：US20240329112A1
公开(公告)日：2024-10-03
申请号：US18130332
申请日：2023-04-03
发明人： Alberto Grassi , Saurabh Surana , Ullas Singh , Namik Kocaman
IPC分类号： G01R31/28 , H03K17/687
CPC分类号： G01R31/2831 , G01R31/2837 , H03K17/687
摘要： A device includes a circuit that generates a first current associated with a voltage of a region of a semiconductor substrate, a second current associated with a temperature of the region, a third current associated with a first process parameter of the region, and a fourth current associated with a second process parameter of the region. A multiplexer of the device receives the first, second, third, and fourth currents and selects the currents one by one and periodically. A ring oscillator of the device is coupled to the multiplexer and receives the first, second, third, and fourth currents one by one and periodically, from the multiplexer. The ring oscillator oscillates at oscillation frequencies that are based on the received current from the multiplexer. The voltage, temperature, and the first and second process parameters of the region are determined based on the oscillation frequencies.
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2.发明公开公开(公告)号：US20230299785A1
公开(公告)日：2023-09-21
申请号：US17700166
申请日：2022-03-21
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
CPC分类号： H03M1/462 , H03M1/0697 , H03M1/468
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). In one aspect, a method includes sampling, by a sample and digital to analog conversion (DAC) circuit, an input voltage to obtain a sampled voltage. The method also includes determining, by a comparator coupled to a set of storage circuits, a state of a plurality of bits corresponding to the sampled voltage. The comparator has a current parameter or voltage parameter adjusted based upon a conversion margin. Adjustment of the current parameter or the voltage parameter affects speed of determining the state of the bits. The method also includes storing the bits in the set of storage circuits. In some aspects, an SAR ADC is configured to perform the method.
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公开(公告)号：US10187080B1
公开(公告)日：2019-01-22
申请号：US15963608
申请日：2018-04-26
发明人： Kumar Thasari , Ullas Singh , Arvindh Iyer , Namik Kocaman
IPC分类号： H03M1/74
摘要： A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.
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公开(公告)号：US10749714B2
公开(公告)日：2020-08-18
申请号：US16236145
申请日：2018-12-28
发明人： Arvindh Iyer , Kumar Thasari , Bo Zhang , Heng Zhang , Jaehun Jeong , Ullas Singh , Namik Kocaman
摘要： Disclosed herein are related to a system and a method for high speed communication. In one aspect, the system includes a set of slicers configured to generate a slicer output signal digitally indicating a level of an input signal received by the set of slicers. The system includes a speculative tap coupled to the set of slicers, where the speculative tap is configured to select bits of the slicer output signal based on selected bits of a prior slicer output signal. The system includes a decoder coupled to the speculative tap, where the decoder is configured to decode the selected bits of the slicer output signal in a first digital representation into a second digital representation. The system includes a feedback generator coupled to the decoder, where the feedback generator is configured to generate a feedback signal according to the decoded bits of the slicer output signal.
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公开(公告)号：US10389377B1
公开(公告)日：2019-08-20
申请号：US16221758
申请日：2018-12-17
发明人： Kumar Thasari , Ullas Singh , Arvindh Iyer , Namik Kocaman
IPC分类号： H03M1/74
摘要： A keeper based switch driver can generate overlapping differential signals and increase a crossing point of the overlapping differential signals a first predetermined amount. Additionally, the keeper based switch driver can further increase the crossing point of the overlapping differential signals a second predetermined amount and limit signal swing to an absolute value of a drain-source voltage. A microprocessor can also be electrically connected to a DAC cell with keeper based switch driver through a performance detection circuit. The microprocessor can be configured to receive information from a performance detection circuit and control a current of a variable current source in a keeper bias circuit accordingly.
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6.发明公开公开(公告)号：US20240097692A1
公开(公告)日：2024-03-21
申请号：US18522698
申请日：2023-11-29
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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7.发明授权公开(公告)号：US11863198B2
公开(公告)日：2024-01-02
申请号：US17699678
申请日：2022-03-21
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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8.发明公开公开(公告)号：US20230299781A1
公开(公告)日：2023-09-21
申请号：US17699678
申请日：2022-03-21
发明人： Ullas Singh , Namik Kocaman , Mohammadamin Torabi , Meisam Honarvar Nazari , Mehmet Batuhan Dayanik , Delong Cui , Jun Cao
IPC分类号： H03M1/06
CPC分类号： H03M1/0697 , H03M1/0678
摘要： Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.
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