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公开(公告)号：US11569830B1
公开(公告)日：2023-01-31
申请号：US17589606
申请日：2022-01-31
发明人： Ahmed Elkholy , Adesh Garg
摘要： A system includes a digital-to-analog converter comprising a plurality of unit elements, and a dynamic element matching encoder coupled to the digital-to-analog converter. The dynamic element matching encoder includes a circuit configured to determine a number of unit elements of a digital-to-analog converter to be transitioned (Ntm), determine a first number of unit elements to be turned on, and determine a second number of unit elements to be turned off. The circuit may further generate a first signal identifying individual unit elements of one or more unit elements of the digital-to-analog converter in the off state to be turned on, and a second signal identifying the individual unit elements of one or more unit elements of the digital-to-analog converter in the on state to be turned off.
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公开(公告)号：US20230268929A1
公开(公告)日：2023-08-24
申请号：US18310737
申请日：2023-05-02
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
CPC分类号： H03M3/50 , H03L7/0991 , H03L7/197
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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公开(公告)号：US20220345152A1
公开(公告)日：2022-10-27
申请号：US17236328
申请日：2021-04-21
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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公开(公告)号：US20240120931A1
公开(公告)日：2024-04-11
申请号：US17964031
申请日：2022-10-11
发明人： Ahmed Elkholy , Jun Cao , Adesh Garg
IPC分类号： H03M1/06
CPC分类号： H03M1/0626
摘要： A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
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公开(公告)号：US20240120905A1
公开(公告)日：2024-04-11
申请号：US17963040
申请日：2022-10-10
发明人： Alireza Nilchi , Adesh Garg , Mohammad Elbadry , Ahmed Elkholy , Jun Cao
摘要： An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.
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公开(公告)号：US20240039483A1
公开(公告)日：2024-02-01
申请号：US17877157
申请日：2022-07-29
发明人： Yousr Ismail , Adesh Garg
IPC分类号： H03F1/48
CPC分类号： H03F1/483
摘要： A circuit for inductive peaking may include a driver, an inverter, a resistor between an output node of the driver and an input node of the inverter and a switch. For example, a first node of the resistor may be connected to the output node of the driver and a second node of the resistor may be connected to the input node of the inverter. The switch may be connected between an output node of the inverter and the first node of the resistor. An input node of the driver may correspond to an input node of the circuit and the output node of the driver may correspond to an output node of the circuit.
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公开(公告)号：US10277210B1
公开(公告)日：2019-04-30
申请号：US15794667
申请日：2017-10-26
发明人： Hyo Gyuem Rhew , Adesh Garg , Meisam Honarvar Nazari , Jiawen Zhang , Ali Nazemi , Jun Cao
摘要： A time-interleaved clock circuit, including circuitry to provide multiple clock components of a sampling clock. The clock components are corrected by averaging pairs of the multiple clock components in order to output averaged signals. The time-interleaved clock is applied to data conversion in which input signals of the analog signal domain or of the digital signal domain are sampled based on the corrected clock components and converted to the digital signal domain or the analog signal domain, respectively.
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公开(公告)号：US12119835B2
公开(公告)日：2024-10-15
申请号：US17964031
申请日：2022-10-11
发明人： Ahmed Elkholy , Jun Cao , Adesh Garg
CPC分类号： H03M1/0626 , H03M1/066 , H03M1/0665 , H03M1/0673 , H03M1/66
摘要： A system includes a first circuit configured to provide a digitally pre-distorted input signal, a digital-to-analog converter including a number of unit elements, a digital input, and a digital output. Each unit element is configured to receive a reference voltage and to be controllable by a control signal provided in response to the digitally pre-distorted input signal. The digital-to-analog converter provides an analog output. The first circuit is configured to reduce distortion due to signal dependent changes to the reference voltage. The signal dependent changes can be due at least in part to current through the supply network that supplies the reference voltage. The digital to analog converter can be a voltage mode converter.
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公开(公告)号：US11683048B2
公开(公告)日：2023-06-20
申请号：US17236328
申请日：2021-04-21
发明人： Ahmed Elkholy , Yousr Ismail , Adesh Garg , Ali Nazemi , Jun Cao
CPC分类号： H03M3/50 , H03L7/0991 , H03L7/00 , H03L7/087 , H03L7/197 , H03L7/1976
摘要： Systems and methods provide a fractional signal from a delta sigma modulator to a summer, a combination of an integer value and the fractional signal to a divider, and a divided clock signal from the divider in response to the combination and the input clock signal. The systems and methods also delay the divided clock signal in response to a truncation phase error and gain calibration factor from a calibration unit to provide an output clock signal having equal periods.
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