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公开(公告)号：US09805683B2
公开(公告)日：2017-10-31
申请号：US14906475
申请日：2015-08-18
发明人： Xing Yao , Seungwoo Han , Yuanbo Zhang
CPC分类号： G09G3/3677 , G09G3/20 , G09G3/3696 , G09G2300/0809 , G09G2310/0267 , G09G2310/0286 , G09G2330/021
摘要： The present invention discloses a Gate-driver-On-Array (GOA) circuit and the driving method thereof and a display device. The GOA circuit comprises a driving module, a low-resolution module and at least two high-resolution modules, the driving module being connected with the low-resolution module and the at least two high-resolution modules respectively; wherein, the driving module is used to output control signal to the low-resolution module and the high-resolution modules; the low-resolution module is used to output a low-resolution signal to at least two rows of pixels under the control of the control signal during low-resolution display; and each high-resolution module is used to output a high-resolution signal to corresponding one row of pixels under the control of the control signal during high-resolution display. The GOA circuit of the present invention may be used to drive multiple rows of pixels and implement the switching between low resolution display and high resolution display.
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公开(公告)号：US11862098B2
公开(公告)日：2024-01-02
申请号：US17628779
申请日：2021-04-09
发明人： Guangliang Shang , Jie Zhang , Shuo Huang , Libin Liu , Shiming Shi , Hao Liu , Haoliang Zheng , Xing Yao
IPC分类号： G09G3/3266 , G09G3/36 , G11C19/28
CPC分类号： G09G3/3266 , G09G3/3677 , G11C19/28 , G09G2300/0852 , G09G2310/0286
摘要： A shift register, a driving method, a driving control circuit and a display device. The method comprises: at a data refresh stage (T10), applying to an input signal end (IP) an input signal having a pulse level, applying a control clock pulse signal to a control clock signal end, and applying a noise reduction clock pulse signal to a noise reduction clock signal end; at a noise reduction holding phase (T21-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a fixed voltage signal to the noise reduction clock signal end; and at a noise reduction enhancement stage (T22-1), applying a fixed voltage signal to the input signal end (IP), applying a fixed voltage signal to the control clock signal end, and applying a clock pulse signal to the noise reduction clock signal end.
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公开(公告)号：US20210335210A1
公开(公告)日：2021-10-28
申请号：US16485994
申请日：2018-09-06
发明人： Mingfu Han , Guangliang Shang , Xing Yao , Haoliang Zheng
IPC分类号： G09G3/32
摘要： The present application discloses a gate driver on array (GOA) circuit of a display panel. The GOA circuit includes a first GOA unit comprising a unit-circuitry structure having a pull-up node commonly coupled to three output transistors to control outputting of a first set of three gate-driving signals respectively to a first set of three gate lines associated with the display panel. The GOA circuit additionally includes a second GOA unit comprising a substantially same unit-circuitry structure cascaded with the first GOA unit and configured to control outputting a second set of three gate-driving signals respectively to a second set of three gate lines associated with the display panel. Moreover, the GOA circuit includes a capacitor connected from one in the second set of three output terminals of the second GOA unit to the pull-up node of the first GOA unit.
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公开(公告)号：US20200258463A1
公开(公告)日：2020-08-13
申请号：US15768309
申请日：2017-10-31
发明人： Jiha Kim , Seungwoo Han , Guangliang Shang , Haoliang Zheng , Xing Yao , Zhichong Wang , Mingfu Han , Lijun Yuan , Yunsik IM , Jing Lv , Xue Dong
摘要： A shift register unit cascaded in a gate drive circuit, wherein the shift register unit comprises: a control circuit configured to output a control signal, at least two buffer circuits coupled to the control circuit, each of the at least two buffer circuits configured to output scan signal to a gate line. As such, the scan signals output from the at least two buffer circuits would be synchronized so that the gate lines respectively coupled to the two buffer circuits can be scanned simultaneously.
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公开(公告)号：US10504469B2
公开(公告)日：2019-12-10
申请号：US15768948
申请日：2017-10-17
发明人： Jiha Kim , Seung Woo Han , Guangliang Shang , Xing Yao , Haoliang Zheng , Mingfu Han , Zhichong Wang , Lijun Yuan , Yun Sik Im , Jing Lv , Yinglong Huang , Xue Dong
IPC分类号： G09G3/36 , G11C19/28 , G09G3/3266 , G09G3/20 , G11C19/18
摘要： A shift-buffer circuit, a gate driving circuit, a display panel, a display device, and a driving method. The shift-buffer circuit includes: a shift register and a plurality of buffers connected with the shift register. The shift register includes a shift output terminal; the shift register is configured to output a shift output signal from the shift output terminal, in response to a shift clock signal; each of the buffers includes a buffer input terminal and a buffer output terminal, the buffer input terminal being connected with the shift output terminal; each of the buffers is configured to output a buffer output signal from the buffer output terminal, in response to a buffer clock signal.
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公开(公告)号：US10475409B2
公开(公告)日：2019-11-12
申请号：US15796463
申请日：2017-10-27
发明人： Mingfu Han , Xing Yao , Guangliang Shang , Haoliang Zheng , Seung-Woo Han , Jiha Kim , Lijun Yuan , Zhichong Wang
摘要： The present disclosure discloses a gate drive circuit, a display panel and a driving method for the gate drive circuit. The gate drive circuit includes a plurality of shift register units connected in cascade; and further includes: buffer units which are in a one-to-one correspondence with shift register units at all levels, and touch control switch units which are in a one-to-one correspondence with shift register units at even levels. Each buffer unit in the gate drive circuit can increase the holding time of the effective pulse signal output by the shift register unit at a corresponding level by one line before resetting, and the effective pulse signal output by a buffer unit at an even level under the control of a touch control unit and the effective pulse signal output by a buffer unit at an adjacent previous odd level are reset at the same time.
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公开(公告)号：US10317758B2
公开(公告)日：2019-06-11
申请号：US14409217
申请日：2014-06-30
发明人： Xing Yao
IPC分类号： H01L27/12 , G02F1/1362 , G02F1/1339 , G02F1/1368
摘要： An array substrate and a display device having the array substrate are provided. The array substrate comprises a display region and a non-display region disposed at the periphery of the display region. The non-display region comprises a gate driver region (GOA region), which comprises a first patterned metal layer formed on a base substrate, a first insulating layer formed on the first patterned metal layer, a second patterned metal layer formed on the first insulating layer, a second insulating layer covering the second patterned metal layer, and a third patterned metal layer formed at a side of the second insulating layer away from the base substrate. The third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.
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公开(公告)号：US10269290B2
公开(公告)日：2019-04-23
申请号：US15680416
申请日：2017-08-18
发明人： Guangliang Shang , Mingfu Han , Haoliang Zheng , Han-Seung- Woo , Im-Yun- Sik , Jing Lv , Yinglong Huang , Jun-Jung- Mok , Xue Dong , Zhichong Wang , Xing Yao , Lijun Yuan , Zhihe Jin
IPC分类号： G09G3/36 , G09G3/20 , G11C19/28 , G09G3/3266
摘要： Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.
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29.发明申请公开(公告)号：US20180301200A1
公开(公告)日：2018-10-18
申请号：US15520191
申请日：2016-11-04
发明人： Guangliang Shang , Seungwoo Han , Mingfu Han , Haoliang Zheng , Xing Yao , Hyunsic Choi
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3677 , G09G2310/0286 , G09G2310/06 , G09G2310/08 , G09G2330/06
摘要： The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
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公开(公告)号：US10096374B2
公开(公告)日：2018-10-09
申请号：US15539220
申请日：2016-11-01
发明人： Guangliang Shang , Seungwoo Han , Haoliang Zheng , Xing Yao , Mingfu Han , Hyunsic Choi , Yunsik Im , Yinglong Huang , Jungmok Jun , Xue Dong
摘要： The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.
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