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    Method of time multiplexing a programmable logic device
    23.
    发明授权
    Method of time multiplexing a programmable logic device 有权
    时间复用可编程逻辑器件的方法

    公开(公告)号：US06480954B2

    公开(公告)日：2002-11-12

    申请号：US09876745

    申请日：2001-06-06

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert Anders Johnson ,  Jennifer Wong

    IPC分类号： G06F900

    CPC分类号： H03K19/17776 ,  G06F17/5054 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/1776

    摘要： A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the interconnect structure. In either embodiment, at least one of the programmable logic elements includes N memory cells. A predetermined one of the N memory cells forms part of a memory slice, wherein at least a portion of each slice of the programmable logic device is allocated to either configuration data or user data memory. Typically, one memory slice provides one configuration of the programmable logic device. In accordance with one embodiment, a memory access port is coupled between at least one of the N memory cells and either one configurable element or the interconnect, thereby facilitating loading of new configuration data into other memory slices during the one configuration. The new configuration data may include off-chip or on-chip data. The present invention typically allocates at least one slice to user data memory and includes means for disabling access to at least one of the N memory cells.

    摘要翻译： 可编程逻辑器件（PLD）包括至少一个可配置元件和用于配置可配置元件的多个可编程逻辑元件。 或者，PLD包括用于配置互连结构的互连结构和多个可编程逻辑元件。 在任一实施例中，至少一个可编程逻辑元件包括N个存储器单元。 N个存储器单元中的预定的一个形成存储器片的一部分，其中可编程逻辑器件的每个片的至少一部分被分配给配置数据或用户数据存储器。 通常，一个存储器片提供可编程逻辑器件的一个配置。 根据一个实施例，存储器访问端口耦合在N个存储器单元中的至少一个和任一个可配置元件或互连之间，从而有助于在一个配置期间将新的配置数据加载到其他存储器片段中。 新的配置数据可以包括片外或片上数据。 本发明通常将至少一个片分配给用户数据存储器，并且包括用于禁止对N个存储器单元中的至少一个的访问的装置。

    Method of time multiplexing a programmable logic device
    24.
    发明授权
    Method of time multiplexing a programmable logic device 失效
    时间复用可编程逻辑器件的方法

    公开(公告)号：US5629637A

    公开(公告)日：1997-05-13

    申请号：US517017

    申请日：1995-08-18

    申请人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    发明人： Stephen M. Trimberger ,  Richard A. Carberry ,  Robert A. Johnson ,  Jennifer Wong

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17752 ,  H03K19/17704 ,  H03K19/17756

    摘要： A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling the identified logic for evaluation in other micro cycles. Alternatively, if the PLD includes a plurality of combinational logic elements, the method further includes scheduling a combinational logic element in a micro cycle no earlier than all the combinational logic elements that generate the input signals to said combinational logic element. Further alternatively, if the PLD includes a plurality of combinational logic elements and a plurality of sequential logic elements, the method further includes scheduling a sequential logic element in a micro cycle no earlier than all the combinational logic elements that generate input signals to the sequential logic element and scheduling each sequential logic element in a micro cycle no earlier than all the combinational logic elements or the sequential logic elements that the sequential logic element drives. If the PLD includes a plurality of combinational logic elements, a plurality of sequential logic elements, and a storage device, the method further includes mapping at least one of the sequential logic elements in the design into the storage device and scheduling the plurality of combinational logic elements and the remaining sequential logic elements.

    摘要翻译： 一种时间复用可编程逻辑器件（PLD）的方法包括输入PLD的设计并将设计逻辑的评估分成多个微循环。 该方法还包括识别不在设计的关键路径内的逻辑，并重新安排所识别的逻辑以在其它微循环中进行评估。 或者，如果PLD包括多个组合逻辑元件，则该方法还包括在不早于生成到所述组合逻辑元件的输入信号的所有组合逻辑元件的微循环中调度组合逻辑元件。 此外，如果PLD包括多个组合逻辑元件和多个顺序逻辑元件，则该方法还包括在不早于生成到顺序逻辑的输入信号的所有组合逻辑元件的微循环中调度顺序逻辑元件 元素，并且在不超过所有组合逻辑元件或顺序逻辑元件驱动的顺序逻辑元件的微循环中调度每个顺序逻辑元件。 如果PLD包括多个组合逻辑元件，多个顺序逻辑元件和存储装置，则该方法还包括将设计中的顺序逻辑元件中的至少一个映射到存储装置中并调度多个组合逻辑 元素和剩余的顺序逻辑元素。

    Combination Local Delivery Using a Stent
    30.
    发明申请
    Combination Local Delivery Using a Stent 审中-公开
    组合使用支架本地交付

    公开(公告)号：US20100092534A1

    公开(公告)日：2010-04-15

    申请号：US12249576

    申请日：2008-10-10

    申请人： Ayala Hezi-Yamit ,  Iskender Matt Bilge ,  Jennifer Wong ,  Carol Sullivan ,  Natividad Vasquez

    发明人： Ayala Hezi-Yamit ,  Iskender Matt Bilge ,  Jennifer Wong ,  Carol Sullivan ,  Natividad Vasquez

    IPC分类号： A61F2/04 ,  A61K31/58 ,  A61K31/4355

    CPC分类号： A61L31/10 ,  A61L31/16 ,  A61L2300/222 ,  A61L2300/416 ,  A61L2300/45

    摘要： Described herein are implantable medical devices useful in treating vascular conditions such as restenosis. In one embodiment, stents are described in which a combination of bioactive agents is described for local delivery in the vasculature. The combination of bioactive agents comprises at least one compound capable of inhibiting smooth muscle cell proliferation and at least one compound capable of mitigating MCP- and/or TF induction. For example, a compound capable of inhibiting smooth muscle cell proliferation is a mTOR inhibitor and a compound capable of mitigating MCP-1 and/or TF induction is a corticosteroid.

    摘要翻译： 本文描述了可用于治疗诸如再狭窄的血管病变的可植入医疗装置。 在一个实施方案中，描述了支架，其中描述了生物活性剂的组合用于脉管系统中的局部递送。 生物活性剂的组合包含至少一种能够抑制平滑肌细胞增殖的化合物和至少一种能够减轻MCP-和/或TF诱导的化合物。 例如，能够抑制平滑肌细胞增殖的化合物是mTOR抑制剂，能够缓解MCP-1和/或TF诱导的化合物是皮质类固醇。