公开(公告)号：US20060286724A1

公开(公告)日：2006-12-21

申请号：US11160361

申请日：2005-06-21

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

公开(公告)号：US20060228862A1

公开(公告)日：2006-10-12

申请号：US10907568

申请日：2005-04-06

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/00

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78 ,  H01L29/7851 ,  H01L2029/7858

摘要： A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with contact pads outside the RX (active silicon conductor) region of the FET.

摘要翻译： 公开了互补金属氧化物半导体场效应晶体管（CMOS FET）的制造布局和制造方法，其提供了长栅极和密集间距，其中栅极触点直接位于栅极的顶部，并且源极和漏极触点被形成接触 CA焊条在FET的RX（有源硅导体）区域外部具有接触焊盘。

公开(公告)号：US20060183289A1

公开(公告)日：2006-08-17

申请号：US11401786

申请日：2006-04-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

公开(公告)号：US20060163673A1

公开(公告)日：2006-07-27

申请号：US11340354

申请日：2006-01-26

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66795

摘要： A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

摘要翻译： 包括隔离层的场效应晶体管（FET），位于隔离层上方的源极区域，位于隔离层上方的漏极区域，位于沟道区域上方的分叉硅化物栅极区域以及邻近栅极的栅氧化层 区，其中所述栅极氧化物层包含以基于通过在所述FET上进行的后硅化物电测试提供的阈值电压测试数据计算的剂量注入的碱金属离子，其中所述碱金属离子包含任何铯和铷。

公开(公告)号：US20060084212A1

公开(公告)日：2006-04-20

申请号：US11200271

申请日：2005-08-09

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.

摘要翻译： 与鳍状场效应晶体管（FinFET）集成的平面基板器件和制造方法包括：包括衬底的绝缘体上硅（SOI）晶片; 衬底上的掩埋绝缘体层; 以及掩埋绝缘体层上的半导体层。 所述结构还包括在所述掩埋绝缘体层上的FinFET和集成在所述衬底中的场效应晶体管（FET），其中所述FET栅极与所述FinFET栅极平面。 该结构还包括在衬底中配置的逆行阱区。 在一个实施例中，该结构还包括在衬底中配置的浅沟槽隔离区域。

公开(公告)号：US20050275922A1

公开(公告)日：2005-12-15

申请号：US10710050

申请日：2004-06-15

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： G02F1/03 ,  G02F1/07 ,  G02F1/19

CPC分类号： G02F1/19 ,  G02F2201/16 ,  G02F2202/34 ,  H01L29/785

摘要： The invention relates to optical switching. Rapid, low-power optical switching is achieved by selectively substantially depleting majority carriers in a plurality of planes of semiconducting material to alter their transmissive response to incoming radiation.

摘要翻译： 本发明涉及光切换。 通过选择性地基本消耗半导体材料的多个平面中的多数载流子来改变其对入射辐射的透射响应来实现快速的低功率光开关。

公开(公告)号：US20050009305A1

公开(公告)日：2005-01-13

申请号：US10604116

申请日：2003-06-26

申请人： Brent Anderson ,  Edward Nowak ,  BethAnn Rainey

发明人： Brent Anderson ,  Edward Nowak ,  BethAnn Rainey

IPC分类号： H01L20060101 ,  H01L21/20 ,  H01L21/324 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/036

CPC分类号： H01L21/02595 ,  H01L21/02667 ,  H01L21/2022 ,  H01L29/66795 ,  H01L29/785

摘要： A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

摘要翻译： 在传统的SOI或体衬底硅器件上提供独立半导体层的方法包括在单晶基底结构上形成非晶或多晶心轴。 然后在心轴和基底结构上形成共形多晶半导体层，其中多晶层接触基底结构。 然后将多晶半导体层重结晶，使其具有与基础结构基本相似的结晶度。 因此，以高度控制其厚度和高度的方式形成独立的半导体层并保持厚度的均匀性。

公开(公告)号：US20070263472A1

公开(公告)日：2007-11-15

申请号：US11382722

申请日：2006-05-11

申请人： Brent Anderson ,  Edward Nowak ,  Noah Zamdmer

发明人： Brent Anderson ,  Edward Nowak ,  Noah Zamdmer

IPC分类号： G11C8/00 ,  H01L21/8234 ,  H01L29/788 ,  H01L21/336

CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined.

摘要翻译： 公开了用于评估过程环境变化的影响的结构和方法。 公开了一种结构和相关方法，其包括以非共线方式布置的多个电结构，用于确定多个电结构附近的工艺环境变化的大小和方向。 多个结构可以包括耦合到第二极性FET的第一极性FET，第一极性FET和第二极性FET中的每一个耦合到第一焊盘和第二焊盘，使得该结构允许独立测量第一极性FET 和仅使用第一和第二焊盘的第二极性FET。 或者，电气结构可以包括电阻器，二极管或环形振荡器。 每个电气结构的适当测量允许确定包括过程环境变化的影响的幅度和方向的梯度场。

公开(公告)号：US20070235818A1

公开(公告)日：2007-10-11

申请号：US11277677

申请日：2006-03-28

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H01L21/823807 ,  H01L21/823828 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78687

摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.

摘要翻译： 本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。 该器件包括在体硅衬底上的鳍式晶体管。 鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。 外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。 诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。 此外，鳍型晶体管在其顶面包括厚氧化物构件。 翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

公开(公告)号：US20070212857A1

公开(公告)日：2007-09-13

申请号：US11749417

申请日：2007-05-16

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/20

CPC分类号： H01L27/1207 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203

摘要： An integrated circuit having devices fabricated in both SOI regions and bulk regions, wherein the regions are connected by a trench filled with epitaxially deposited material. The filled trench provides a continuous semiconductor surface joining the SOI and bulk regions. The SOI and bulk regions may have the same or different crystal orientations. The present integrated circuit is made by forming a substrate with SOI and bulk regions separated by an embedded sidewall spacer (made of dielectric). The sidewall spacer is etched, forming a trench that is subsequently filled with epitaxial material. After planarizing, the substrate has SOI and bulk regions with a continuous semiconductor surface. A butted P-N junction and silicide layer can provide electrical connection between the SOI and bulk regions.

摘要翻译： 具有在SOI区域和体区域中制造的器件的集成电路，其中所述区域通过填充有外延沉积材料的沟槽连接。 填充的沟槽提供连接SOI和块区域的连续的半导体表面。 SOI和体区可以具有相同或不同的晶体取向。 本集成电路通过形成具有由嵌入式侧壁间隔物（由电介质制成）隔开的SOI和主体区域的衬底制成。 蚀刻侧壁间隔物，形成随后用外延材料填充的沟槽。 在平坦化之后，衬底具有SOI和具有连续半导体表面的体区。 对接的P-N结和硅化物层可以在SOI和体区之间提供电连接。