公开(公告)号：US08426901B2

公开(公告)日：2013-04-23

申请号：US13166867

申请日：2011-06-23

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US07989854B2

公开(公告)日：2011-08-02

申请号：US11094623

申请日：2005-03-30

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US07952151B2

公开(公告)日：2011-05-31

申请号：US12950064

申请日：2010-11-19

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L29/41

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

摘要翻译： 半导体器件可以包括衬底，衬底的有源半导体区域和栅电极。 有源半导体区域可以包括在第一和第二连接区域之间的沟道区域。 沟道区可以包括第一半导体材料，第一和第二结区可以包括第二半导体材料，并且第一和第二半导体材料可以是不同的。 栅电极可以在沟道区上，其中第一和第二结区的部分没有栅电极。

公开(公告)号：US20100038702A1

公开(公告)日：2010-02-18

申请号：US12588071

申请日：2009-10-02

申请人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun park ,  Dong-won Kim

发明人： Chang-woo Oh ,  Sung-hwan Kim ,  Dong-gun park ,  Dong-won Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/7887 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/42332

摘要： Example embodiments relate to a semiconductor memory device and methods of forming the same. Other example embodiments relate to a nonvolatile memory device and methods of forming the same. The memory device may include memory cells separately formed on a channel region between impurity regions formed on a substrate. The memory cells may each include a memory layer having a tunnel insulating layer, a nano-sized charge storage layer, and a blocking insulating layer and a side gate formed on the memory layer. According to example embodiments, larger scale integration of the nonvolatile memory devices may be achieved and the reliability of the memory devices may increase.

摘要翻译： 示例性实施例涉及半导体存储器件及其形成方法。 其他示例实施例涉及非易失性存储器件及其形成方法。 存储器件可以包括分别形成在形成在衬底上的杂质区域之间的沟道区上的存储器单元。 存储单元可各自包括具有隧道绝缘层，形成在存储层上的绝缘层，纳米尺寸电荷存储层以及阻挡绝缘层和侧栅极的存储层。 根据示例实施例，可以实现非易失性存储器件的更大比例的集成，并且存储器件的可靠性可能增加。

公开(公告)号：US20060029887A1

公开(公告)日：2006-02-09

申请号：US11094623

申请日：2005-03-30

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Ming Li ,  Sung-hwan Kim

IPC分类号： G03F7/00

CPC分类号： H01L29/66833 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66795 ,  H01L29/785

摘要： Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

摘要翻译： 半导体器件包括具有从半导体衬底突出并被隔离结构包围的堆叠结构的半导体衬底。 堆叠结构包括半导体衬底和有源层图案之间的有源层图案和间隙填充绝缘层。 栅电极围绕堆叠结构从隔离结构延伸。 栅电极被配置为提供用于有源层图案的支撑结构。 栅电极可以是形成在半导体晶片上的绝缘体上硅（SOI）器件的栅电极，并且半导体器件还可以包括在半导体衬底的形成在半导体衬底上的体积硅器件， 保护层。

公开(公告)号：US20060022268A1

公开(公告)日：2006-02-02

申请号：US11190254

申请日：2005-07-26

申请人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

发明人： Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Sung-dae Suk

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843

摘要： A semiconductor device may include a substrate and a fin shaped semiconductor region on the substrate. The fin shaped semiconductor region may include a channel region and first and second junction regions on opposite sides of the channel region. A gate electrode may be provided on the channel region of the fin shaped semiconductor region, and a stress inducing layer on the fin shaped semiconductor region.

摘要翻译： 半导体器件可以包括衬底和衬底上的鳍状半导体区域。 鳍状半导体区域可以包括沟道区域和在沟道区域的相对侧上的第一和第二结区域。 可以在鳍状半导体区域的沟道区域上设置栅电极，在鳍状半导体区域上设置应力感应层。

公开(公告)号：US20050176219A1

公开(公告)日：2005-08-11

申请号：US11050557

申请日：2005-02-03

申请人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

发明人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

IPC分类号： H01L21/336 ,  C30B1/00 ,  H01L29/06

CPC分类号： H01L29/0653 ,  H01L29/0649 ,  H01L29/6659

摘要： A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.

摘要翻译： 可以通过在牺牲晶体结构的上表面上和衬底上生长外延半导体层以形成掩埋牺牲结构来形成金属氧化物半导体场效应晶体管（MOSFET）。 可以去除掩埋的牺牲结构以形成空穴而不是埋入的牺牲结构，并且可以在空隙中形成器件隔离层。

公开(公告)号：US07605025B2

公开(公告)日：2009-10-20

申请号：US11050557

申请日：2005-02-03

申请人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

发明人： Min-sang Kim ,  Chang-woo Oh ,  Dong-won Kim ,  Kyoung-hwan Yeo ,  Sung-min Kim

IPC分类号： H01L21/00 ,  H01L21/76

CPC分类号： H01L29/0653 ,  H01L29/0649 ,  H01L29/6659

摘要： A Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) can be formed by growing an epitaxial semiconductor layer on an upper surface of a sacrificial crystalline structure and on a substrate to form a buried sacrificial structure. The buried sacrificial structure can be removed to form a void in place of the buried sacrificial structure and a device isolation layer can be formed in the void.

摘要翻译： 可以通过在牺牲晶体结构的上表面上和衬底上生长外延半导体层以形成掩埋牺牲结构来形成金属氧化物半导体场效应晶体管（MOSFET）。 可以去除掩埋的牺牲结构以形成空穴而不是埋入的牺牲结构，并且可以在空隙中形成器件隔离层。

公开(公告)号：US20100059807A1

公开(公告)日：2010-03-11

申请号：US12461500

申请日：2009-08-13

申请人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

发明人： Keun-hwl Cho ,  Dong-won Kim ,  Jun Seo ,  Min-sang Kim ,  Sung-min Kim ,  Hyun-jun Bae ,  Ji-Myoung Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/66795 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10879 ,  H01L29/785

摘要： A semiconductor device having a bar type active pattern and a method of manufacturing the same are provided. The semiconductor device may include a semiconductor substrate having a semiconductor fin configured to protrude from a surface of the semiconductor substrate in a first direction, the semiconductor substrate having a first width and a second width crossing the first width, wherein the first width and the second width extend in a second direction. A plurality of active patterns may be arranged in the first direction with a separation gap from the semiconductor fin. A plurality of support patterns may be arranged between the semiconductor fin and one of the plurality of active patterns arranged closer to the semiconductor fin in the first direction, and between the plurality of active patterns arranged in the first direction to support the plurality of active patterns. A gate may be arranged to cross the plurality of active patterns in the second direction and to cover a portion of the at least one of the plurality of active patterns.

摘要翻译： 提供了具有条形有源图案的半导体器件及其制造方法。 半导体器件可以包括具有半导体鳍片的半导体衬底，半导体鳍片被配置为在第一方向上从半导体衬底的表面突出，半导体衬底具有与第一宽度交叉的第一宽度和第二宽度，其中第一宽度和第二宽度 宽度在第二方向上延伸。 多个有源图案可以在第一方向上与半导体鳍片分离间隙布置。 多个支撑图案可以布置在半导体翅片与沿着第一方向布置得更靠近半导体鳍片的多个有源图案中的一个之间以及沿着第一方向布置的多个有源图案之间，以支撑多个有源图案 。 栅极可以布置成在第二方向上跨越多个有源图案并且覆盖多个有源图案中的至少一个的一部分。

公开(公告)号：US20090275177A1

公开(公告)日：2009-11-05

申请号：US12503594

申请日：2009-07-15

申请人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

发明人： Ming Li ,  Kyoung-hwan Yeo ,  Sung-min Kim ,  Sung-dae Suk ,  Dong-won Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L29/1083 ,  H01L29/66787

摘要： A semiconductor device with multiple channels includes a semiconductor substrate and a pair of conductive regions spaced apart from each other on the semiconductor substrate and having sidewalls that face to each other. A partial insulation layer is disposed on the semiconductor substrate between the conductive regions. A channel layer in the form of at least two bridges contacts the partial insulation layer, the at least two bridges being spaced apart from each other in a first direction and connecting the conductive regions with each other in a second direction that is at an angle relative to the first direction. A gate insulation layer is on the channel layer, and a gate electrode layer on the gate insulation layer and surrounding a portion of the channel layer.

摘要翻译： 具有多个通道的半导体器件包括半导体衬底和在半导体衬底上彼此间隔开并且具有彼此面对的侧壁的一对导电区域。 在导电区域之间的半导体衬底上设置有部分绝缘层。 至少两个桥的形式的沟道层接触部分绝缘层，所述至少两个桥在第一方向上彼此间隔开，并且在与第一方向相反的第二方向上将导电区彼此连接 到第一个方向。 栅极绝缘层在沟道层上，栅极电极层在栅极绝缘层上并围绕沟道层的一部分。