公开(公告)号：US09558957B2

公开(公告)日：2017-01-31

申请号：US13894890

申请日：2013-05-15

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Francois Andrieu ,  Sebastien Barnola ,  Jerome Belledent

IPC: H01L21/308 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/8234

CPC classification number: H01L21/3088 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L21/823431

Abstract: A substrate is successively provided with a support (7), an electrically insulating layer (8), and a semi-conductor material layer (2). A first protective mask (1) completely covers a second area (B) of the semi-conductor material layer and leaves a first area (A) of the semi-conductor material layer uncovered. A second etching mask (3) partially covers the first area (A) and at least partially covers the second area (B), so as to define and separate a first area and a second area. Lateral spacers are formed on the lateral surfaces of the second etching mask (3) so as to form a third etching mask. The semi-conductor material layer (2) is etched by means of the third etching mask so as to form a pattern made from semi-conductor material in the first area (A), the first etching mask (3) protecting the second area (B).

Abstract translation: 基板依次设置有支撑体（7），电绝缘层（8）和半导体材料层（2）。 第一保护掩模（1）完全覆盖半导体材料层的第二区域（B）并且留下未覆盖的半导体材料层的第一区域（A）。 第二蚀刻掩模（3）部分地覆盖第一区域（A）并且至少部分地覆盖第二区域（B），以便限定和分离第一区域和第二区域。 在第二蚀刻掩模（3）的侧表面上形成横向间隔件，以形成第三蚀刻掩模。 通过第三蚀刻掩模蚀刻半导体材料层（2），以在第一区域（A）中形成由半导体材料制成的图案，第一蚀刻掩模（3）保护第二区域 B）。

公开(公告)号：US20150097241A1

公开(公告)日：2015-04-09

申请号：US14505570

申请日：2014-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Richard ,  Francois Andrieu

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603

Abstract: The transverse mechanical stress within the active region of a MOS transistor is relaxed by forming an insulating incursion, such as an insulated trench, within the active region of the MOS transistor. The insulated incursion is provided at least in a channel region of the MOS transistor so as to separate the channel region into two parts. The insulated incursion is configured to extend in a direction of a length of the MOS transistor. The insulated incursion may further extend into one or more of a source region or drain region located adjacent the channel region of the MOS transistor.

Abstract translation: MOS晶体管的有源区内的横向机械应力通过在MOS晶体管的有源区内形成诸如绝缘沟槽的绝缘侵入来松弛。 绝缘侵入至少在MOS晶体管的沟道区域中提供，以将沟道区分成两部分。 绝缘侵入被配置为在MOS晶体管的长度方向上延伸。 绝缘侵入可以进一步延伸到与MOS晶体管的沟道区相邻的源区或漏区中的一个或多个。