-
公开(公告)号：US11112459B2
公开(公告)日：2021-09-07
申请号：US16022989
申请日：2018-06-29
Applicant: Credo Technology Group Limited
Inventor： Haoli Qian , Yifei Dai , Ruiqing Sun
IPC: G01R31/3185
Abstract: A method for testing operation of a device under test (DUT) includes receiving an input bit stream at an input pin, the input bit stream including multiplexed test patterns for a plurality of scan chains of the DUT. The method further includes demultiplexing the multiplexed test patterns, and providing a corresponding test pattern data to each of the plurality of scan chains. The method further includes, at each of the plurality of scan chains, scanning test results from the scan chain, to produce multiplex output test data into an output bit stream.
-
公开(公告)号：US20210243050A1
公开(公告)日：2021-08-05
申请号：US17237250
申请日：2021-04-22
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeffey Twombly
IPC: H04L12/46 , H04B3/46 , H04L12/40 , H04L12/751 , H04L12/935
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
-
公开(公告)号：US10411917B2
公开(公告)日：2019-09-10
申请号：US15831092
申请日：2017-12-04
Applicant: Credo Technology Group Limited
Inventor： Haoli Qian , Haihui Luo
Abstract: A linear feedback equalizer includes comparators that digitize incoming analog signals. The equalizer further includes digital-to-analog converters (“DACs”) that transform a current digitized signal into one or more feedback analog signals. The equalizer further includes a subtractor that subtracts the feedback analog signals from the output of a continuous-time linear equalizer (“CTLE”) and provides the difference to the comparators as incoming analog signals.
-
公开(公告)号：US10063305B2
公开(公告)日：2018-08-28
申请号：US15365579
申请日：2016-11-30
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
CPC classification number: H04B7/0632 , H04L1/16 , H04L1/203 , H04L1/242 , H04L1/244 , H04L45/123
Abstract: Illustrative communications link performance analyzer methods and modules that accommodate FEC. In at least some embodiments, a method for characterizing communications link performance includes: (A) transmitting a predetermined bit stream across a physical communications link to produce a receive signal; (B) deriving a received bit stream from the receive signal with a receiver, the receiver including an embedded debug module having: (1) a bit counter dividing the received bit stream into symbols and frames; (2) an error counter determining a symbol error count for each frame; and (3) an aggregator obtaining at least one performance-related statistic from the symbol error counts; (C) generating a performance measure based on the at least one performance-related statistic; and (D) displaying a visual representation of the performance measure.
-
公开(公告)号：US11570024B2
公开(公告)日：2023-01-31
申请号：US17453066
申请日：2021-11-01
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Fang Cai , Junqing (Phil) Sun , Haoli Qian
Abstract: Equalization methods and equalizers employing discrete-time filters are provided with dynamic perturbation effect based adaptation. Tap coefficient values may be individually perturbed during the equalization process and the effects on residual ISI monitored to estimate gradient components or rows of a difference matrix. The gradient or difference matrix components may be assembled and filtered to obtain components suitable for calculating tap coefficient updates with reduced adaptation noise. The dynamic perturbation effect based updates may be interpolated with precalculated perturbation effect based updates to enable faster convergence with better accommodation of analog component performance changes attributable to variations in process, supply voltage, and temperature.
-
Patent Agency Ranking
公开(公告)号：US11347476B2
公开(公告)日：2022-05-31
申请号：US17067056
申请日：2020-10-09
Applicant: Credo Technology Group Limited
Inventor： Tianchen Luo , Junqing Sun , Haoli Qian
Abstract: Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.
-
公开(公告)号：US11309995B2
公开(公告)日：2022-04-19
申请号：US16793746
申请日：2020-02-18
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Junqing Sun , Haoli Qian
Abstract: Digital communication transmitters, systems, and methods can introduce skew into parallel transmission channels to enhance the performance of forward error correction (FEC) decoders. One illustrative serializer-deserializer (SerDes) transmitter embodiment includes: a block code encoder configured to convert a sequence of input data blocks into a sequence of encoded data blocks; a demultiplexer configured to distribute code symbols from the sequence of encoded data blocks to multiple lanes in a cyclical fashion, the multiple lanes corresponding to parallel transmission channels; a skewer configured to buffer the multiple lanes to provide respective lane delays, the lane delays differing from each other by no less than half an encoded data block period; and multiple drivers, each driver configured to transmit code symbols from one of said multiple lanes on a respective one of said parallel transmission channels.
-
公开(公告)号：US11231740B2
公开(公告)日：2022-01-25
申请号：US16269491
申请日：2019-02-06
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Fang Cai , Junqing Sun , Haoli Qian
Abstract: Disclosed clock recovery modules provide improved performance with only limited complexity and power requirements. In one illustrative embodiment, a clock recovery method includes: oversampling a receive signal to obtain mid-symbol interval (MSI) samples and between-symbol interval (BSI) samples; processing at least the MSI samples to obtain symbol decisions; filtering the symbol decisions to obtain BSI targets; determining a timing error based on a difference between the BSI samples and the BSI targets; and deriving from the timing error a clock signal for said oversampling.
-
公开(公告)号：US20210399941A1
公开(公告)日：2021-12-23
申请号：US16904074
申请日：2020-06-17
Applicant: Credo Technology Group Limited
Inventor： Calvin Xiong Fang , Haoli Qian , Ashwin Upadhya
IPC: H04L12/24 , H04L12/707 , H04L12/26
Abstract: An illustrative embodiment of a disclosed physical layer interface device includes: a first transmitter and a first receiver for a primary data path; a second transmitter and a second receiver for a secondary data path; a third transmitter and a third receiver for a non-redundant data path; and a multiplexer. The third receiver is coupled to provide a data stream received from the non-redundant data path concurrently to the first and second transmitters, and the multiplexer provides the third transmitter with a selected one of the data stream received via the primary data path and the data stream received via the secondary data path. Disclosed network switch embodiments employ the illustrative physical layer interface to provide internal or external data path redundancy for traffic handled by the network switch.
-
公开(公告)号：US11032103B2
公开(公告)日：2021-06-08
申请号：US16084277
申请日：2017-03-08
Applicant: Credo Technology Group Limited
Inventor： Yifei Dai , Haoli Qian , Jeff Twombly
IPC: H04L12/46 , H04B3/46 , H04L12/40 , H04L12/751 , H04L12/935
Abstract: Ethernet link extension methods and devices provide, in one illustrative embodiment, an Ethernet link extender with physical medium attachment (PMA) circuits each having a transmitter and receiver that communicate with a respective node in a sequence of communication phases. The sequence includes at least an auto-negotiation phase and a subsequent training phase, the phases occurring simultaneously for both PMA circuits. In the auto-negotiation phase, the PMA circuits operate in a pass-through mode, rendering the extender transparent to the two nodes. In the training phase, the PMA circuits operate independently, sending training frames to their respective nodes based in part on received back-channel information and locally-determined training status information. The training phases may be prolonged if needed to provide a simultaneous transition to a frame-forwarding phase of the sequence.
-
-
-
-
-
-
-
-
-
Search Results
31
records
(took 0.017 seconds)
