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28 条记录 (耗时 0.019 秒)

    Bidirectional PNPN silicon-controlled rectifier
    21.
    发明申请
    Bidirectional PNPN silicon-controlled rectifier 有权
    双向PNPN可控硅整流器

    公开(公告)号：US20090236631A1

    公开(公告)日：2009-09-24

    申请号：US12076556

    申请日：2008-03-20

    申请人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

    发明人： Wen-Yi Chen ,  Ryan Hsin-Chin Jiang ,  Ming-Dou Ker

    IPC分类号： H01L29/747

    CPC分类号： H01L27/0262 ,  H01L29/747 ,  H01L29/87

    摘要： The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.

    摘要翻译： 本发明公开了一种双向PNPN可控硅整流器，包括：p型衬底; N型外延层; 所有形成在N型外延层内的P型阱和两个N型阱，两个N型阱分别布置在P型阱的两侧; 所述第一半导体区域，第二半导体区域和第三半导体区域全部形成在所述P型阱内并全部耦合到阳极，其中所述第二半导体区域和所述第三半导体区域分别布置在所述第一半导体区域的第二半导体区域 并且其中所述第一半导体区域是第一导电类型，并且所述第二半导体区域和所述第三半导体区域是第二导电类型; 分别形成在N型阱内部的两个P型掺杂区域，其中每个P型掺杂区域具有与P型阱相邻的第四半导体区域和第五半导体区域，并且其中第四半导体区域和第五半导体区域 半导体区域耦合到阴极，并且其中第四半导体区域是第二导电类型，并且第五半导体区域是第一导电类型。

    Transient voltage detection circuit
    23.
    发明授权
    Transient voltage detection circuit 有权
    瞬态电压检测电路

    公开(公告)号：US08116049B2

    公开(公告)日：2012-02-14

    申请号：US12625449

    申请日：2009-11-24

    申请人： Ming-Dou Ker ,  Hsin-Chin Jiang ,  Wen-Yi Chen

    发明人： Ming-Dou Ker ,  Hsin-Chin Jiang ,  Wen-Yi Chen

    IPC分类号： H02H3/22

    CPC分类号： H02H9/046 ,  H02H1/0007

    摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.

    摘要翻译： 本发明公开了一种适用于电子系统的瞬态电压检测电路。 电子系统包括高压线路和低压线路。 瞬态电压检测电路包括至少一个检测电路和判断模块。 每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。 晶体管与电容器耦合，检测节点位于晶体管和电容器之间。 判断模块耦合到每个检测节点。 判断模块根据检测节点的电压电平生成判断。 因此，形成了瞬态电压检测电路。 电子系统可以根据判断选择性地执行保护动作。

    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
    25.
    发明授权
    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface 有权
    用于混合电压I / O接口的高耐压电源轨ESD钳位电路

    公开(公告)号：US07397280B2

    公开(公告)日：2008-07-08

    申请号：US11366143

    申请日：2006-03-02

    申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

    发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

    IPC分类号： H03K19/0175

    CPC分类号： H01L27/0266

    摘要： A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

    摘要翻译： 用于静电放电（ESD）保护的电路包括电阻器，与电阻器串联连接的电容器，包括栅极的第一晶体管，栅极连接到第一电源，通过电阻向栅极提供第一电压，第一 端子连接到第一电源，第二晶体管包括栅极，栅极连接到第二电源，第二电源提供小于第一电压的第二电压，第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管，栅极连接到第二电源，第三晶体管的第一端子连接到第二晶体管的第二端子，第二端子连接到第二晶体管， 参考电压不同于第一电压和第二电压。

    Method and monitor structure for detecting and locating IC wiring defects
    26.
    发明授权
    Method and monitor structure for detecting and locating IC wiring defects 有权
    IC接线缺陷检测和定位的方法和监控结构

    公开(公告)号：US07317203B2

    公开(公告)日：2008-01-08

    申请号：US11189180

    申请日：2005-07-25

    申请人： Wen-Yi Chen ,  Jun-Yean Chiu ,  Chung Lee ,  Hung-Hon Lui

    发明人： Wen-Yi Chen ,  Jun-Yean Chiu ,  Chung Lee ,  Hung-Hon Lui

    IPC分类号： H01L23/58 ,  H01L21/66

    CPC分类号： H01L22/32 ,  H01L22/14 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A 3-dimensional PCM structure and method for using the same for carrying out 3-dimensional integrated circuit wiring electrical testing and failure analysis in an integrated circuit manufacturing process, the method including forming a first metallization layer; carrying out a first wafer acceptance testing (WAT) process to test the electrical continuity of the first metallization layer; forming first metal vias on the first metallization layer conductive portions and a second metallization layer comprising metal islands on the first metal vias wherein the metal islands electrically communicate with the first metallization layer to form a process control monitor (PCM) structure; and, carrying out a second WAT process to test the electrical continuity of the first metallization layer.

    摘要翻译： 一种用于在集成电路制造工艺中进行三维集成电路布线电气测试和故障分析的三维PCM结构及其方法，所述方法包括形成第一金属化层; 执行第一晶片验收测试（WAT）过程以测试第一金属化层的电连续性; 在所述第一金属化层导电部分上形成第一金属通孔，以及在所述第一金属通孔上形成包含金属岛的第二金属化层，其中所述金属岛与所述第一金属化层电连通以形成过程控制监视器（PCM）结构; 以及进行第二WAT处理以测试第一金属化层的电连续性。

    High-voltage tolerant power rail electrostatic discharge clamp circuit
    27.
    发明授权
    High-voltage tolerant power rail electrostatic discharge clamp circuit 有权
    高耐压电力轨道静电放电钳位电路

    公开(公告)号：US07283342B1

    公开(公告)日：2007-10-16

    申请号：US11428571

    申请日：2006-07-05

    申请人： Ming-Dou Ker ,  Wen-Yi Chen

    发明人： Ming-Dou Ker ,  Wen-Yi Chen

    IPC分类号： H02H9/00 ,  H02H3/20 ,  H02H3/22

    CPC分类号： H01L27/0285

    摘要： A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.

    摘要翻译： 提出了一种高耐压电源轨ESD钳位电路，其中电路器件可以在没有栅极氧化可靠性问题的工艺限制的三倍大的高电源电压下安全工作。 此外，ESD检测电路用于通过基板触发技术有效地提高整个ESD保护功能。 由于仅使用低电压（1 * VDD）器件来实现高电压（3 * VDD）公差的目标，所以提出的设计为具有混合电压接口的芯片提供了具有成本效益的电源轨ESD保护解决方案。

    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface
    28.
    发明申请
    High-voltage tolerant power-rail ESD clamp circuit for mixed-voltage I/O interface 有权
    用于混合电压I / O接口的高耐压电源轨ESD钳位电路

    公开(公告)号：US20070205800A1

    公开(公告)日：2007-09-06

    申请号：US11366143

    申请日：2006-03-02

    申请人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

    发明人： Ming-Dou Ker ,  Wen-Yi Chen ,  Che-Hao Chuang

    IPC分类号： H03K19/003

    CPC分类号： H01L27/0266

    摘要： A circuit for electrostatic discharge (ESD) protection includes a resistor a capacitor connected in series with the resistor, a first transistor including a gate, the gate being connected to a first power supply providing a first voltage to the gate via the resistor and a first terminal connected to the first power supply, a second transistor including a gate, the gate being connected to a second power supply, the second power supply providing a second voltage smaller than the first voltage, the second transistor having a first terminal connected to a second terminal of the first transistor, and a third transistor including a gate, the gate being connected to the second power supply, a first terminal of the third transistor being connected to a second terminal of the second transistor, and a second terminal being connected to a reference voltage different from the first voltage and the second voltage.

    摘要翻译： 用于静电放电（ESD）保护的电路包括电阻器，与电阻器串联连接的电容器，包括栅极的第一晶体管，栅极连接到第一电源，通过电阻向栅极提供第一电压，第一 端子连接到第一电源，第二晶体管包括栅极，栅极连接到第二电源，第二电源提供小于第一电压的第二电压，第二晶体管具有连接到第二电源的第一端子 第一晶体管的端子和包括栅极的第三晶体管，栅极连接到第二电源，第三晶体管的第一端子连接到第二晶体管的第二端子，第二端子连接到第二晶体管， 参考电压不同于第一电压和第二电压。