公开(公告)号：US07565558B2

公开(公告)日：2009-07-21

申请号：US11409974

申请日：2006-04-25

Applicant: Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

Inventor： Wen Juin Huang ,  Chung-Ching Huang ,  Hao Lin Lin ,  Yeh Cho

IPC: G06F1/00 ,  G06F1/32 ,  G06F13/00

CPC classification number: G06F1/3203

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract translation: 公开了一种省电方法及其系统。 当中央处理单元处于非窥探睡眠状态并且外围设备发送总线主机请求时，芯片将驱动中央处理单元从非窥探睡眠状态唤醒并进入用于执行中断服务的系统管理模式 使中央处理单元处于停止状态的程序。 然后中央处理单元被驱动以进入窥探睡眠状态以窥探总线主控请求。 执行总线主机请求后，芯片将驱动中央处理单元离开窥探睡眠状态，并返回到非窥探睡眠状态，以实现功耗节省。

公开(公告)号：US07296185B2

公开(公告)日：2007-11-13

申请号：US10820768

申请日：2004-04-09

Applicant: Chung-Ching Huang ,  Hao-Lin Lin

Inventor： Chung-Ching Huang ,  Hao-Lin Lin

IPC: G06F11/00

CPC classification number: G06F11/362

Abstract: A debugging device and method are provided, including a central processing unit (CPU) connected to a chipset with a system management interrupt pin. The debugging method includes sending out a system management interrupt signal to central processing unit from the system management interrupt pin of the chipset. Then the CPU moves into a system management mode and pops out a debugging operation window for selecting and executing each debugging item. After the execution of each debugging item is completed, the CPU will leave the debugging operation window and return to the next instruction before debugging. After the execution of each debugging item is completed in the debugging operation window, the CPU will return to the operation system and continue the execution of next instruction before debugging. The execution of debugging will not influence the status and the program execution from the operating system. The disclosed debugging method is convenient for executing each debugging item at any time.

Abstract translation: 提供了一种调试设备和方法，包括连接到具有系统管理中断引脚的芯片组的中央处理单元（CPU）。 调试方法包括从芯片组的系统管理中断引脚向中央处理单元发送系统管理中断信号。 然后CPU进入系统管理模式，并弹出一个调试操作窗口，用于选择和执行每个调试项目。 每个调试项目的执行完成后，CPU将离开调试操作窗口，并在调试前返回到下一条指令。 在调试操作窗口中完成每个调试项目的执行后，CPU将返回到操作系统，并在调试之前继续执行下一条指令。 调试的执行不会影响操作系统的状态和程序的执行。 所公开的调试方法可以随时执行每个调试项目。

公开(公告)号：US07293167B2

公开(公告)日：2007-11-06

申请号：US10965405

申请日：2004-10-14

Applicant: Yeh Cho ,  Chung-Ching Huang

Inventor： Yeh Cho ,  Chung-Ching Huang

IPC: G06F9/00 ,  G06F15/177 ,  G06F1/24

CPC classification number: G06F3/0632 ,  G06F3/0607 ,  G06F3/0676 ,  G06F9/4411

Abstract: A method and apparatus for driving a non-native SATA hard disk applied in a computer is provided. The computer includes a basic input/output system (BIOS) and an operating system (OS), both of which support an advanced configuration and power interface (ACPI). The non-native SATA hard disk includes a conversion interface and a parallel ATA (PATA) internal disk. First, issue an interrupt. Then, process an interrupt handle routine for detecting and saving the timing mode of the PATA internal disk. Next, load a default IDE driver. Then, report the saved timing mode. Finally, set the SATA hard disk according to the timing mode.

Abstract translation: 提供了一种用于驱动应用在计算机中的非本机SATA硬盘的方法和装置。 该计算机包括基本的输入/输出系统（BIOS）和操作系统（OS），两者都支持高级配置和电源接口（ACPI）。 非本机SATA硬盘包括转换接口和并行ATA（PATA）内部磁盘。 首先发出中断。 然后处理一个中断处理程序，用于检测和保存PATA内部磁盘的定时模式。 接下来，加载默认的IDE驱动程序。 然后，报告保存的定时模式。 最后，根据定时模式设置SATA硬盘。

公开(公告)号：US08769256B2

公开(公告)日：2014-07-01

申请号：US13110098

申请日：2011-05-18

Applicant: Chin-Hwaun Wu ,  Chung-Ching Huang ,  Kuo-Han Chang ,  Tai-Yu Lin

Inventor： Chin-Hwaun Wu ,  Chung-Ching Huang ,  Kuo-Han Chang ,  Tai-Yu Lin

IPC: G06F9/24 ,  G06F1/32

CPC classification number: G06F9/4893 ,  G06F1/3275 ,  G06F1/329 ,  G06F9/461 ,  Y02D10/14 ,  Y02D10/24

Abstract: An operating system switching method is provided. The operating system switching method is for a computer system comprising a control unit, a memory unit, and a storage unit, wherein the storage unit comprises a first operating system and a second operating system. The steps of the method include: loading the first operating system and the second operating system into a first memory space and a second memory space of the memory unit, respectively, and setting the first memory space and the second memory space to a working state and a standby state, respectively; and performing a first switching of the operating systems, and setting the first memory space and the second memory space to the standby state and the working state.

Abstract translation: 提供了一种操作系统切换方法。 操作系统切换方法是用于包括控制单元，存储单元和存储单元的计算机系统，其中存储单元包括第一操作系统和第二操作系统。 该方法的步骤包括：分别将第一操作系统和第二操作系统加载到存储器单元的第一存储器空间和第二存储器空间中，并将第一存储器空间和第二存储器空间设置为工作状态， 分别为待机状态; 以及执行所述操作系统的第一切换，以及将所述第一存储器空间和所述第二存储器空间设置为待机状态和所述工作状态。

公开(公告)号：US08650425B2

公开(公告)日：2014-02-11

申请号：US12774041

申请日：2010-05-05

Applicant: Chung-Ching Huang ,  Yeh Cho ,  Kuo-Han Chang ,  Liang-Min Lee ,  Donna Lim

Inventor： Chung-Ching Huang ,  Yeh Cho ,  Kuo-Han Chang ,  Liang-Min Lee ,  Donna Lim

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/32 ,  G06F11/3055

Abstract: A computer system for processing data in a non-operational state and processing method thereof are provided. The computer system includes a data output unit, a data source, a data processing module and a state monitor unit. The data processing module accesses and processes data from the data source, and transmits the processed data to the data output unit. The state monitor unit monitors a power supply state of the computer system to generate a state switch signal, which indicates whether the computer system is in an operational state or a non-operational state. When the state switch signal indicates that the computer system is in a non-operational state, the data source and the data processing module receives operating voltages to access and process data.

Abstract translation: 提供了一种用于处理非操作状态的数据的计算机系统及其处理方法。 计算机系统包括数据输出单元，数据源，数据处理模块和状态监视单元。 数据处理模块从数据源访问和处理数据，并将处理的数据发送到数据输出单元。 状态监视器单元监视计算机系统的电源状态以产生状态切换信号，其指示计算机系统是处于操作状态还是非操作状态。 当状态切换信号指示计算机系统处于非操作状态时，数据源和数据处理模块接收操作电压以访问和处理数据。

公开(公告)号：US08108598B2

公开(公告)日：2012-01-31

申请号：US12416605

申请日：2009-04-01

Applicant: Chung-Ching Huang ,  Chin-Han Chang ,  Jia-Hung Wang

Inventor： Chung-Ching Huang ,  Chin-Han Chang ,  Jia-Hung Wang

IPC: G06F13/00

CPC classification number: G06F13/385

Abstract: A hard drive assessing method and a hard drive assessing system supporting a maximum transmission rate of a hard drive are provided, wherein the hard drive is accessed by a controller, and both the controller and the hard drive support a plurality of transmission rates. The maximum transmission rate of the hard drive is first obtained. When the controller reads data from the hard drive, the transmission rate of the controller is set to be not lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. When the controller writes data into the hard drive, the transmission rate of the controller is reduced to be lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. Thereby, the hard drive can be accessed at its maximum transmission rate.

Abstract translation: 提供了硬盘驱动器评估方法和支持硬盘驱动器的最大传输速率的硬盘驱动器评估系统，其中硬盘驱动器被控制器访问，并且控制器和硬盘驱动器都支持多个传输速率。 首先获得硬盘驱动器的最大传输速率。 当控制器从硬盘驱动器读取数据时，将控制器的传输速率设置为不低于最大传输速率，并将硬盘驱动器的传输速率保持在最大传输速率。 当控制器将数据写入硬盘驱动器时，控制器的传输速率降低到低于最大传输速率，硬盘驱动器的传输速率保持在最大传输速率。 因此，可以以其最大传输速率访问硬盘驱动器。

公开(公告)号：US07802119B2

公开(公告)日：2010-09-21

申请号：US11707966

申请日：2007-02-20

Applicant: Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

Inventor： Wen-Juin Huang ,  Chung-Ching Huang ,  Jui-Ming Wei

IPC: G06F1/00 ,  G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3243 ,  Y02D10/152

Abstract: For saving power of a central processing unit at a C3 power level upon processing a bus master request from a peripheral device, an arbitrator is disabled from transmitting any request to the central processing unit at the C3 power level. Afterwards, in response to a bus master request, the central processing unit is switched from the C3power level to a transitional C0 power level while keeping the arbitrator disabled, and then switched from the transitional C0 power level to a C2 power level while enabling the arbitrator to process the bus master request.

Abstract translation: 为了在从外围设备处理总线主机请求时以C3功率电平节省中央处理单元的功率，仲裁器被禁止在C3功率电平向中央处理单元发送任何请求。 之后，响应于总线主机请求，中央处理单元从C3power电平切换到过渡C0功率电平，同时保持仲裁器禁用，然后从过渡C0功率电平切换到C2功率电平，同时启用仲裁器 处理总线主机请求。

公开(公告)号：US07363408B2

公开(公告)日：2008-04-22

申请号：US11000300

申请日：2004-11-30

Applicant: Tony Ho ,  Chung-Ching Huang ,  Norman Chung

Inventor： Tony Ho ,  Chung-Ching Huang ,  Norman Chung

IPC: G06F13/24

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: An interruption control system includes an interruption message generator, a stop clock control module and an interruption status indicating path. The interruption message generator is used for decoding and identifying a message signaled interrupt (MSI) issued by a first peripheral device or a second peripheral device when interruption is to be conducted, and generates an interruption status indicating message in response to the message signaled interrupt (MSI). The stop clock control module is coupled to the interruption message generator and the CPU and de-asserts a stop clock signal that is previously asserted to have the CPU enter a power-saving state to have the CPU deactivate the power-saving state in response to the interruption status indicating message. The interruption status indicating path is used for transmitting the interruption status indicating message.

Abstract translation: 中断控制系统包括中断消息发生器，停止时钟控制模块和中断状态指示路径。 所述中断消息发生器用于在进行中断时解码和识别由第一外围设备或第二外围设备发出的消息信号中断（MSI），并响应于消息信号中断产生中断状态指示消息（ MSI）。 停止时钟控制模块耦合到中断消息发生器和CPU，并且取消断言先前断言的停止时钟信号，以使CPU进入省电状态，以使CPU能够响应于CPU 中断状态指示消息。 中断状态指示路径用于发送中断状态指示消息。

公开(公告)号：US20070162772A1

公开(公告)日：2007-07-12

申请号：US11409974

申请日：2006-04-25

Applicant: Wen Huang ,  Chung-Ching Huang ,  Hao Lin ,  Yeh Cho

Inventor： Wen Huang ,  Chung-Ching Huang ,  Hao Lin ,  Yeh Cho

IPC: G06F1/00

CPC classification number: G06F1/3203

Abstract: A power saving method and system thereof is disclosed. When the central processing unit is under a non-snooping sleep state and a peripheral device sends a bus master request, a chip will drive the central processing unit waking from the non-snooping sleep state and entering a system management mode for executing an interrupt service routine that makes the central processing unit in halt status. The central processing unit is then driven to enter a snooping sleep state for snooping the bus master request. After the execution of the bus master request, the chip will drive the central processing unit to leave the snooping sleep state and return to the non-snooping sleep state for power consumption conservation.

Abstract translation: 公开了一种省电方法及其系统。 当中央处理单元处于非窥探睡眠状态并且外围设备发送总线主机请求时，芯片将驱动中央处理单元从非窥探睡眠状态唤醒并进入用于执行中断服务的系统管理模式 使中央处理单元处于停止状态的程序。 然后中央处理单元被驱动以进入窥探睡眠状态以窥探总线主控请求。 执行总线主机请求后，芯片将驱动中央处理单元离开窥探睡眠状态，并返回到非窥探睡眠状态，以实现功耗节省。

公开(公告)号：US20070157039A1

公开(公告)日：2007-07-05

申请号：US11505973

申请日：2006-08-18

Applicant: Wen-Juin Huang ,  Chung-Ching Huang

Inventor： Wen-Juin Huang ,  Chung-Ching Huang

IPC: G06F1/00

CPC classification number: G06F1/3228

Abstract: A power saving method applied to a central processing unit under a non-snooping sleeping state with a bus master request from a peripheral device is presented. In accordance with the present invention, first prohibit the central processing unit from fetching instruction. Then drive the central processing unit entering a snooping sleeping state and enabling the arbiter for transferring the bus master request to the central processing unit. After the central processing unit completes the bus master request, the arbiter is disabled and the central processing unit is driven to leave the snooping sleeping state and return back to the non-snooping sleeping state. Therefore, the power consumed by the central processing unit is reduced so as to save power.

Abstract translation: 提出了一种在具有来自外围设备的总线主机请求的非窥探睡眠状态下应用于中央处理单元的省电方法。 根据本发明，首先禁止中央处理单元取出指令。 然后驱动中央处理单元进入窥探睡眠状态，并允许仲裁器将总线主控请求传送到中央处理单元。 中央处理单元完成总线主机请求后，仲裁器被禁止，中央处理单元被驱动离开窥探休眠状态并返回到非窥探睡眠状态。 因此，中央处理单元消耗的功率降低，从而节省功率。