公开(公告)号：US06207504B1

公开(公告)日：2001-03-27

申请号：US09223337

申请日：1998-12-30

申请人： Alex Hsieh ,  Chun-Ming Wu ,  Chih-Hung Lin

发明人： Alex Hsieh ,  Chun-Ming Wu ,  Chih-Hung Lin

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.

摘要翻译： 一种制造闪存可擦除可编程只读存储器的方法。 提供具有隔离结构的基板。 在衬底上依次形成隧道氧化物层和浮栅，并进行图案化。 进行离子注入并且在衬底中形成第一掺杂区域。 执行氧化步骤以在衬底上形成第一氧化物层。 在衬底上依次形成氮化物/氧化物层和控制栅极层。 对控制栅极层，氮化物/氧化物层，第一氧化物层和浮置栅极层进行图案化，直到基板露出为止。 执行离子注入步骤以在衬底中形成公共源极区域和漏极区域。 间隔件形成在控制栅极层，氮化物/氧化物层，第一氧化物层和浮动栅极层的侧壁上。 执行自对准硅化物步骤以在控制栅极层，公共源极区域和漏极区域上形成硅化物层。

公开(公告)号：US5716874A

公开(公告)日：1998-02-10

申请号：US603248

申请日：1996-02-20

申请人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

发明人： Joe Ko ,  Gary Hong ,  Chih-Hung Lin

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

摘要翻译： 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层，由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模，衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗（通孔）。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上，沉积和限定金属接触层以覆盖绝缘体。

公开(公告)号：USD910408S1

公开(公告)日：2021-02-16

申请号：US29708162

申请日：2019-10-03

申请人： Chih-Hung Lin

设计人： Chih-Hung Lin

公开(公告)号：US20190230895A1

公开(公告)日：2019-08-01

申请号：US15884432

申请日：2018-01-31

申请人： Chih-Hung Lin ,  Li- Wen Shen

发明人： Chih-Hung Lin ,  Li- Wen Shen

IPC分类号： A01K1/03 ,  A01K1/035

CPC分类号： A01K1/033 ,  A01K1/035

摘要： A pet combination house includes a housing and a connecting unit. The housing includes a plurality of plates, with a folding line being formed at a connection of two plates. The plates are folded upward along the folding line and are connected together to construct the housing. Some of the plates have a side respectively provided with a fastening member. The fastening members of the plates are detachably combined together in pairs when the housing is disposed at the three-dimensional state. At least one of the plates is provided with an opening. At least one of the plates has a face provided with a plurality of apertures. The connecting unit includes a plurality of retaining members mounted on the plates and aligning with the apertures, and a plurality of connecting members mounted in the apertures and retained by the retaining members.

公开(公告)号：US20180192804A1

公开(公告)日：2018-07-12

申请号：US15399830

申请日：2017-01-06

申请人： Chih-Hung Lin

发明人： Chih-Hung Lin

IPC分类号： A47G23/02 ,  B32B27/06 ,  B32B5/18 ,  B65D81/38

CPC分类号： A47G23/0216 ,  A47G23/0241 ,  B32B5/18 ,  B32B27/06 ,  B32B2323/043 ,  B32B2323/046 ,  B32B2439/00 ,  B65D81/3886

摘要： A foldable container sleeve adapted to sleeve around a container includes a sleeve body for sleeving around the container. The sleeve body includes an insulating layer for wrapping around and contacting the container, a laminating layer disposed along and connected to an exterior surface of the insulating layer, and a smooth layer disposed along and connected to an exterior surface of the laminating layer. The insulating layer is made of a polyethylene foam material, the laminating layer is made of a polyethylene material, and the smooth layer is made of a thermoplastic material.

公开(公告)号：US08786815B2

公开(公告)日：2014-07-22

申请号：US13330627

申请日：2011-12-19

申请人： Chih-Hung Lin ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Che-Chia Chang ,  Sheng-Chao Liu ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Maw-Song Chen

发明人： Chih-Hung Lin ,  Wu-Liu Tsai ,  Chuan-Sheng Wei ,  Che-Chia Chang ,  Sheng-Chao Liu ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Maw-Song Chen

IPC分类号： G02F1/133 ,  G02F1/1368

CPC分类号： G02F1/133707 ,  G02F1/136213 ,  G02F2201/40

摘要： A display panel having a display region and a non-display region is provided. The display panel includes a plurality of pixel structures in the display region, and each pixel structure includes a scan line, a data line, a first active device, a pixel electrode, a first insulating layer, a capacitor electrode, and a second insulating layer. The first active device includes a first gate, a first channel, a first source, and a first drain. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the first drain. At least one driving circuit is disposed in the non-display region and includes at least one second active device. Hence, a relatively thin insulating layer can be disposed between the capacitor electrode and the drain to reduce the area of the capacitor region and to achieve a desired aperture ratio.

摘要翻译： 提供具有显示区域和非显示区域的显示面板。 显示面板包括显示区域中的多个像素结构，并且每个像素结构包括扫描线，数据线，第一有源器件，像素电极，第一绝缘层，电容器电极和第二绝缘层 。 第一有源器件包括第一栅极，第一沟道，第一源极和第一漏极。 第二绝缘层覆盖第一绝缘层和电容器电极，并且位于电容器电极和第一漏极之间。 至少一个驱动电路设置在非显示区域中并且包括至少一个第二有源器件。 因此，可以在电容器电极和漏极之间设置相对薄的绝缘层，以减小电容器区域的面积并实现所需的孔径比。

公开(公告)号：US08650567B2

公开(公告)日：2014-02-11

申请号：US13287650

申请日：2011-11-02

申请人： Zhi-Wei Chen ,  Chia-Wei Tien ,  Chin-Wei Tien ,  Chih-Hung Lin

发明人： Zhi-Wei Chen ,  Chia-Wei Tien ,  Chin-Wei Tien ,  Chih-Hung Lin

IPC分类号： G06F9/455

CPC分类号： G06F21/53 ,  G06F9/45558 ,  G06F11/3093 ,  G06F2009/45587 ,  G06F2201/815 ,  G06F2201/865

摘要： A virtual machine monitoring method used in a virtual machine monitoring system is provided. The virtual machine monitoring method includes retrieving a hypercall transmitted from one of a plurality of virtual machines to a hypervisor of a virtual machine monitoring system, wherein the hypercall is used for establishing a channel between a source virtual machine and a target virtual machine. A central control virtual machine ID information in the hypervisor is retrieved. A type of the channel established by the hypercall is determined according to the central control virtual machine ID information and channel-establishing information corresponding to the hypercall. When the channel is a private channel that is not related to a central control virtual machine of the virtual machines, a security module is used to monitor the private channel.

摘要翻译： 提供了虚拟机监控系统中使用的虚拟机监控方法。 所述虚拟机监视方法包括检索从多个虚拟机中的一个发送到虚拟机监视系统的管理程序的超级呼叫，其中，所述超级呼叫用于在源虚拟机和目标虚拟机之间建立通道。 检索管理程序中的中央控制虚拟机ID信息。 根据中心控制虚拟机ID信息和对应于该超级呼叫的信道建立信息来确定由超级呼叫建立的信道类型。 当信道是与虚拟机的中央控制虚拟机无关的专用信道时，使用安全模块来监视专用信道。

公开(公告)号：USD691802S1

公开(公告)日：2013-10-22

申请号：US29438984

申请日：2012-12-05

申请人： Chih-Hung Lin

设计人： Chih-Hung Lin

公开(公告)号：US08471973B2

公开(公告)日：2013-06-25

申请号：US12788876

申请日：2010-05-27

申请人： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

发明人： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC分类号： G02F1/36

CPC分类号： G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

摘要： This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

摘要翻译： 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20130126871A1

公开(公告)日：2013-05-23

申请号：US13402883

申请日：2012-02-23

申请人： Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

发明人： Chuan-Sheng Wei ,  Chau-Shiang Huang ,  Wu-Liu Tsai ,  Chih-Hung Lin ,  Maw-Song Chen

IPC分类号： H01L33/58

CPC分类号： H01L33/58 ,  G02F1/136213 ,  G02F1/136227 ,  H01L27/1255

摘要： A pixel structure includes a first electrode on a substrate, a first insulation layer covering the first electrode, a gate located on the first insulation layer, a second electrode located on the first insulation layer above the first electrode, a second insulation layer covering the gate and the second electrode, a semiconductor layer located on the second insulation layer above the gate, a source and a drain that are located on the semiconductor layer, a third electrode, a third insulation layer, and a pixel electrode. The third electrode is located on the second insulation layer above the second electrode and electrically connected to the first electrode. The third insulation layer covers the source, the drain, and the third electrode. The pixel electrode is located on the third insulation layer and electrically connected to the drain.

摘要翻译： 像素结构包括在基板上的第一电极，覆盖第一电极的第一绝缘层，位于第一绝缘层上的栅极，位于第一电极上方的第一绝缘层上的第二电极，覆盖栅极的第二绝缘层 并且第二电极，位于栅极上方的第二绝缘层上的半导体层，位于半导体层上的源极和漏极，第三电极，第三绝缘层和像素电极。 第三电极位于第二电极上方的第二绝缘层上并与第一电极电连接。 第三绝缘层覆盖源极，漏极和第三电极。 像素电极位于第三绝缘层上并与漏极电连接。