Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric
    21.
    发明授权
    Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric 有权
    具有高K电介质的半导体器件具有渐变介电常数的间隔物

    公开(公告)号:US06764966B1

    公开(公告)日:2004-07-20

    申请号:US10085278

    申请日:2002-02-27

    IPC分类号: H01L2128

    摘要: A semiconductor device formed on a semiconductor substrate having an active region and a method of making the same is disclosed. The semiconductor device includes a dielectric layer interposed between a gate electrode and the semiconductor substrate. Further, the semiconductor device includes graded dielectric constant spacers formed on sidewalls of the dielectric layer, sidewalls of the gate electrode and portions of an upper surface of the semiconductor substrate. The dielectric constant of the graded dielectric constant spacers decreases in a direction away from the sidewalls of the dielectric layer.

    摘要翻译: 公开了一种形成在具有有源区的半导体衬底上的半导体器件及其制造方法。 半导体器件包括插入在栅电极和半导体衬底之间的电介质层。 此外,半导体器件包括形成在电介质层的侧壁,栅电极的侧壁和半导体衬底的上表面的部分上的渐变介电常数间隔物。 梯度介电常数间隔物的介电常数在远离介电层的侧壁的方向上减小。

    Process for preventing deformation of patterned photoresist features
    23.
    发明授权
    Process for preventing deformation of patterned photoresist features 有权
    防止图案化光刻胶特征变形的方法

    公开(公告)号:US06589709B1

    公开(公告)日:2003-07-08

    申请号:US09819692

    申请日:2001-03-28

    IPC分类号: G03F700

    CPC分类号: H01L21/28123

    摘要: A process for preventing deformation of patterned photoresist features during integrated circuit fabrication is disclosed herein. The process includes stabilizing the patterned photoresist features by a flood electron beam before one or more etch processes. The stabilized patterned photoresist features resist pattern bending, breaking, collapsing, or deforming during a given etch process. The electron beam stabilization can be applied to the patterned photoresist features a plurality of times as desired.

    摘要翻译: 本文公开了在集成电路制造期间防止图案化光致抗蚀剂特征变形的方法。 该方法包括在一个或多个蚀刻工艺之前通过泛洪电子束稳定图案化的光致抗蚀剂特征。 稳定的图案化光刻胶特征在给定的蚀刻工艺期间抵抗图案弯曲,断裂,塌陷或变形。 电子束稳定可根据需要多次施加到图案化的光致抗蚀剂特征。

    Process for fabricating a semiconductor device component by oxidizing a silicon hard mask
    24.
    发明授权
    Process for fabricating a semiconductor device component by oxidizing a silicon hard mask 有权
    通过氧化硅硬掩模来制造半导体器件部件的工艺

    公开(公告)号:US06323093B1

    公开(公告)日:2001-11-27

    申请号:US09290088

    申请日:1999-04-12

    IPC分类号: H01L21336

    CPC分类号: H01L21/28123

    摘要: A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques, followed by an oxidation process to reduce the lateral dimension of the hard-mask. The oxidation process is carried out by selectively oxidizing an oxidizable layer overlying an etch-stop layer. Upon completion of the oxidation process, the etch-stop layer is removed and a residual layer of oxidizable material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

    摘要翻译: 制造半导体器件的方法包括使用光刻技术形成硬掩模,随后进行氧化处理以减小硬掩模的横向尺寸。 通过选择性地氧化覆盖在蚀刻停止层上的可氧化层来进行氧化过程。 氧化工艺完成后,去除蚀刻停止层,然后使用剩余的可氧化材料层作为形成器件部件的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

    Process for fabricating a semiconductor device component using a selective silicidation reaction
    25.
    发明授权
    Process for fabricating a semiconductor device component using a selective silicidation reaction 有权
    使用选择性硅化反应制造半导体器件部件的工艺

    公开(公告)号:US06211044B1

    公开(公告)日:2001-04-03

    申请号:US09290087

    申请日:1999-04-12

    IPC分类号: H01L213205

    CPC分类号: H01L21/28123 H01L29/6659

    摘要: A process for fabricating a semiconductor device includes the formation of a hard-mask using lithographic techniques followed by a selective silicidation reaction process to reduce the lateral dimension of the hard-mask. The silicidation reaction is carried out by selectively reacting a reaction layer situated between an etch-stop layer and a reaction resistant layer. Upon completion of the chemical reaction process, the etch-stop layer and the reaction resistant layer is removed, and a residual layer of unreacted material is then used as a mask for the formation of a device component. The lateral dimension of the residual layer can be substantially less than that achievable by optical lithographic techniques.

    摘要翻译: 制造半导体器件的方法包括使用光刻技术形成硬掩膜,然后进行选择性硅化反应工艺以减小硬掩模的横向尺寸。 通过选择性地使位于蚀刻停止层和反应层之间的反应层反应来进行硅化反应。 化学反应过程完成后,除去蚀刻停止层和反应层,然后使用残留的未反应材料层作为形成器件组分的掩模。 残余层的横向尺寸可以显着小于通过光学平版印刷技术实现的尺寸。

    Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal
    29.
    发明授权
    Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal 有权
    包括高K栅极电介质的晶体管栅极的制造工艺,其具有原位抗蚀剂修整,栅极蚀刻和高K电介质去除

    公开(公告)号:US06790782B1

    公开(公告)日:2004-09-14

    申请号:US10157450

    申请日:2002-05-29

    IPC分类号: H01L21302

    摘要: The invention provides a method of small geometry gate formation on the surface of a high-K gate dielectric. The method provides for processing steps that include gate pattern trimming, gate stack etch, and removal of exposed regions of the high-K dielectric to be performed efficiently in a single etch chamber. As such, process complexity and processing costs are reduced while throughput and overall process efficiency is improved. The method includes fabricating a high-K gate dielectric etch stop dielectric layer on the surface of a silicon substrate to protect the silicon substrate from erosion during an etch step and to prove a gate dielectric. A polysilicon layer is fabricated above the high-K dielectric layer. An anti-reflective coating layer above the polysilicon layer, and a mask is fabricated above the anti-reflective coating layer to define a gate region and an erosion region. The sequence of etching steps discussed above are performed in-situ in an enclosed high density plasma etching chamber environment.

    摘要翻译: 本发明提供了在高K栅极电介质的表面上形成小几何形状的栅极的方法。 该方法提供了处理步骤,其包括在单个蚀刻室中有效执行的栅极图案修整,栅极堆叠蚀刻和去除高K电介质的暴露区域。 因此,降低了处理复杂性和处理成本,同时提高了吞吐量和整体处理效率。 该方法包括在硅衬底的表面上制造高K栅电介质蚀刻阻挡介电层,以在蚀刻步骤期间保护硅衬底免受腐蚀并证明栅极电介质。 在高K电介质层上方制造多晶硅层。 在多晶硅层上方的抗反射涂层和在抗反射涂层上方制造掩模以限定栅极区域和侵蚀区域。 上述蚀刻步骤的顺序在封闭的高密度等离子体蚀刻室环境中原位进行。

    Method for forming fins in a FinFET device using sacrificial carbon layer
    30.
    发明授权
    Method for forming fins in a FinFET device using sacrificial carbon layer 有权
    在使用牺牲碳层的FinFET器件中形成翅片的方法

    公开(公告)号:US06645797B1

    公开(公告)日:2003-11-11

    申请号:US10310926

    申请日:2002-12-06

    IPC分类号: H01L2184

    CPC分类号: H01L29/785 H01L29/66795

    摘要: A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further includes etching the mask and carbon layer to form at least one structure, where the structure has a first width, reducing the width of the carbon layer in the at least one structure to a second width, depositing an oxide layer to surround the at least one structure, removing a portion of the oxide layer and the mask, removing the carbon layer to form an opening in a remaining portion of the oxide layer for each of the at least one structure, filling the at least one opening with conductive material, and removing the remaining portion of the oxide layer and a portion of the conductive layer to form the fin.

    摘要翻译: 一种在半导体器件中形成翅片的方法,包括:衬底,形成在衬底上的绝缘层和形成在绝缘层上的导电层,包括在导电层上形成碳层,并在碳层上形成掩模 。 该方法还包括蚀刻掩模和碳层以形成至少一种结构,其中结构具有第一宽度,将至少一个结构中的碳层的宽度减小到第二宽度,沉积氧化物层以围绕 至少一个结构,去除所述氧化物层和所述掩模的一部分,除去所述碳层以在所述至少一个结构中的每一个结构的氧化物层的剩余部分中形成开口,用导电材料填充所述至少一个开口 并且去除氧化物层的剩余部分和导电层的一部分以形成翅片。