Method for controlling disk-tray ejection
    21.
    发明申请
    Method for controlling disk-tray ejection 审中-公开
    控制盘托盘排出的方法

    公开(公告)号:US20050219968A1

    公开(公告)日:2005-10-06

    申请号:US11096581

    申请日:2005-04-01

    IPC分类号: G11B7/085 G11B17/04 G11B19/12

    CPC分类号: G11B19/124 G11B17/056

    摘要: A method for controlling disk-tray ejection in an optical disk apparatus is provided. The optical disk apparatus includes a control unit and a tray that supports a disk. The method includes the steps of: (a) determining the diameter value of the disk; (b) driving the tray by the control unit with a first driving force to process the disk ejection procedure if the diameter value is a first length; and (c) driving the tray by the control unit with a second driving force to process the disk ejection procedure if the diameter is not the first length.

    摘要翻译: 提供了一种用于控制光盘装置中盘盘排出的方法。 光盘装置包括控制单元和支撑盘的托盘。 该方法包括以下步骤:(a)确定盘的直径值; (b)如果所述直径值是第一长度,则利用所述控制单元用所述第一驱动力驱动所述托盘以处理所述盘喷射程序; 和(c)如果直径不是第一长度,则用第二驱动力由控制单元驱动托盘以处理盘排出程序。

    Fabrication method for a two-bit flash memory cell
    22.
    发明授权
    Fabrication method for a two-bit flash memory cell 失效
    两位闪存单元的制造方法

    公开(公告)号:US06303439B1

    公开(公告)日:2001-10-16

    申请号:US09449297

    申请日:1999-11-24

    IPC分类号: H01L218247

    摘要: A method for fabricating a two-bit flash memory cell is described in which a substrate with a trench formed therein is provided. A conformal tunnel oxide layer is then formed on the substrate, followed by forming polysilicon spacers on the portion of the tunnel oxide layer which covers the sidewalls of the trench. The polysilicon spacers are separated into a first polysilicon spacer on the right sidewall and a second polysilicon spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the polysilicon spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.

    摘要翻译: 描述了一种用于制造双位闪存单元的方法,其中提供了形成有沟槽的衬底。 然后在衬底上形成保形隧道氧化物层,随后在覆盖沟槽侧壁的隧道氧化物层的部分上形成多晶硅间隔物。 多晶硅间隔物被分离成右侧壁上的第一多晶硅间隔物和左侧壁上的第二多晶硅间隔物。 此后,在多晶硅间隔物上形成栅极氧化层,随后在衬底的栅极氧化物层上形成多晶硅栅极。 随后,在衬底中的多晶硅栅极的两侧上形成源/漏区。

    Method of fabricating flash erasable programmable read only memory
    23.
    发明授权
    Method of fabricating flash erasable programmable read only memory 失效
    制造闪存可擦写可编程只读存储器的方法

    公开(公告)号:US06207504B1

    公开(公告)日:2001-03-27

    申请号:US09223337

    申请日:1998-12-30

    IPC分类号: H01L21336

    CPC分类号: H01L27/11521 H01L27/115

    摘要: A method of fabricating flash erasable programmable read only memory. A substrate having an isolation structure is provided. A tunnel oxide layer and a floating gate layer are formed in sequence over substrate and are patterned. An ion implantation is performed and a first doped region is formed in the substrate. An oxidation step is performed to form a first oxide layer over the substrate. A nitride/oxide layer and a control gate layer are formed in sequence over the substrate. The control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer are patterned until the substrate is exposed. An ion implantation step is performed to form a common source region and a drain region in the substrate. Spacers are formed over the sidewalls of the control gate layer, the nitride/oxide layer, the first oxide layer, and the floating gate layer. A self-aligned silicide step is performed to form silicide layers over the control gate layer, the common source region, and the drain region.

    摘要翻译: 一种制造闪存可擦除可编程只读存储器的方法。 提供具有隔离结构的基板。 在衬底上依次形成隧道氧化物层和浮栅,并进行图案化。 进行离子注入并且在衬底中形成第一掺杂区域。 执行氧化步骤以在衬底上形成第一氧化物层。 在衬底上依次形成氮化物/氧化物层和控制栅极层。 对控制栅极层,氮化物/氧化物层,第一氧化物层和浮置栅极层进行图案化,直到基板露出为止。 执行离子注入步骤以在衬底中形成公共源极区域和漏极区域。 间隔件形成在控制栅极层,氮化物/氧化物层,第一氧化物层和浮动栅极层的侧壁上。 执行自对准硅化物步骤以在控制栅极层,公共源极区域和漏极区域上形成硅化物层。

    Method of fabricating EPROM memory by individually forming gate oxide
and coupling insulator
    24.
    发明授权
    Method of fabricating EPROM memory by individually forming gate oxide and coupling insulator 失效
    通过单独形成栅氧化物和耦合绝缘体来制造EPROM存储器的方法

    公开(公告)号:US5716874A

    公开(公告)日:1998-02-10

    申请号:US603248

    申请日:1996-02-20

    IPC分类号: H01L21/336 H01L21/8247

    CPC分类号: H01L29/66825

    摘要: A method of fabricating an EPROM memory increases a coupling ratio and reduces lateral diffusion by forming a gate oxide layer and a coupling insulator individually. A substrate is provided with a field oxide layer to isolate a predetermined active area. A gate oxide layer is formed on the substrate. On the field oxide layer and the gate oxide layer, a polysilicon layer is deposited and defined, whereby a portion of this polysilicon layer and gate oxide layer form a gate electrode. Using the gate electrode as a mask, the substrate is implanted with impurities to provide source and drain electrodes. A dielectric layer is formed on polysilicon layer. A contact window (via) is formed in a predetermined area of dielectric layer. An insulator is deposited and defined by etching, on dielectric layer and the contact window. On the insulator and dielectric layer, a metal contact layer is deposited and defined to cover the insulator.

    摘要翻译: 制造EPROM存储器的方法通过单独形成栅极氧化物层和耦合绝缘体来增加耦合比并减小横向扩散。 衬底设置有场氧化物层以隔离预定的有效面积。 在衬底上形成栅氧化层。 在场氧化物层和栅极氧化物层上沉积并限定多晶硅层,由此该多晶硅层和栅极氧化物层的一部分形成栅电极。 使用栅电极作为掩模,衬底被注入杂质以提供源极和漏极。 介电层形成在多晶硅层上。 在电介质层的预定区域中形成接触窗(通孔)。 通过在电介质层和接触窗上进行蚀刻来沉积并限定绝缘体。 在绝缘体和电介质层上,沉积和限定金属接触层以覆盖绝缘体。

    Pet Combination House that is Assembled and Disassembled Quickly to Facilitate Storage

    公开(公告)号:US20190230895A1

    公开(公告)日:2019-08-01

    申请号:US15884432

    申请日:2018-01-31

    IPC分类号: A01K1/03 A01K1/035

    CPC分类号: A01K1/033 A01K1/035

    摘要: A pet combination house includes a housing and a connecting unit. The housing includes a plurality of plates, with a folding line being formed at a connection of two plates. The plates are folded upward along the folding line and are connected together to construct the housing. Some of the plates have a side respectively provided with a fastening member. The fastening members of the plates are detachably combined together in pairs when the housing is disposed at the three-dimensional state. At least one of the plates is provided with an opening. At least one of the plates has a face provided with a plurality of apertures. The connecting unit includes a plurality of retaining members mounted on the plates and aligning with the apertures, and a plurality of connecting members mounted in the apertures and retained by the retaining members.

    Foldable Container Sleeve
    27.
    发明申请

    公开(公告)号:US20180192804A1

    公开(公告)日:2018-07-12

    申请号:US15399830

    申请日:2017-01-06

    申请人: Chih-Hung Lin

    发明人: Chih-Hung Lin

    摘要: A foldable container sleeve adapted to sleeve around a container includes a sleeve body for sleeving around the container. The sleeve body includes an insulating layer for wrapping around and contacting the container, a laminating layer disposed along and connected to an exterior surface of the insulating layer, and a smooth layer disposed along and connected to an exterior surface of the laminating layer. The insulating layer is made of a polyethylene foam material, the laminating layer is made of a polyethylene material, and the smooth layer is made of a thermoplastic material.

    Driving circuit and display panel having the same
    28.
    发明授权
    Driving circuit and display panel having the same 有权
    驱动电路和显示面板相同

    公开(公告)号:US08786815B2

    公开(公告)日:2014-07-22

    申请号:US13330627

    申请日:2011-12-19

    IPC分类号: G02F1/133 G02F1/1368

    摘要: A display panel having a display region and a non-display region is provided. The display panel includes a plurality of pixel structures in the display region, and each pixel structure includes a scan line, a data line, a first active device, a pixel electrode, a first insulating layer, a capacitor electrode, and a second insulating layer. The first active device includes a first gate, a first channel, a first source, and a first drain. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the first drain. At least one driving circuit is disposed in the non-display region and includes at least one second active device. Hence, a relatively thin insulating layer can be disposed between the capacitor electrode and the drain to reduce the area of the capacitor region and to achieve a desired aperture ratio.

    摘要翻译: 提供具有显示区域和非显示区域的显示面板。 显示面板包括显示区域中的多个像素结构,并且每个像素结构包括扫描线,数据线,第一有源器件,像素电极,第一绝缘层,电容器电极和第二绝缘层 。 第一有源器件包括第一栅极,第一沟道,第一源极和第一漏极。 第二绝缘层覆盖第一绝缘层和电容器电极,并且位于电容器电极和第一漏极之间。 至少一个驱动电路设置在非显示区域中并且包括至少一个第二有源器件。 因此,可以在电容器电极和漏极之间设置相对薄的绝缘层,以减小电容器区域的面积并实现所需的孔径比。

    Pixel designs of improving the aperture ratio in an LCD
    30.
    发明授权
    Pixel designs of improving the aperture ratio in an LCD 有权
    像素设计提高了LCD中的开口率

    公开(公告)号:US08471973B2

    公开(公告)日:2013-06-25

    申请号:US12788876

    申请日:2010-05-27

    IPC分类号: G02F1/36

    摘要: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

    摘要翻译: 本发明在一个方面涉及像素结构。 在一个实施例中,像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线,形成在衬底上的像素区域内的开关,形成在开关上的屏蔽电极,有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极,以及具有从第一部分延伸的第一部分和第二部分的像素电极,并且形成在屏蔽电极和平面有机层的上方 像素区域,其中第一部分与屏蔽电极重叠以便在其间限定存储电容器,并且第二部分覆盖平面有机层并且不与数据线重叠。