摘要:
In one illustrative embodiment, the method includes providing a wafer including at least one non-production area, forming a process layer above the wafer, forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and performing a process operation on the exposed portion of the process layer formed above the at least one non-production area. In another aspect, the present invention is directed to a system that includes a controller for identifying at least one non-production area of a wafer, a photolithography tool for forming a masking layer above the process layer, the masking layer being patterned so as to expose a portion of the process layer formed above the at least one non-production area, and an etch tool for performing an etching process on the exposed portion of the process layer formed above the at least one non-production area.
摘要:
A method and an apparatus for affecting dispatch and/or disposition of a workpiece. A process step upon a workpiece is performed based upon a predetermined routing plan. An end-of-line parameter is modeled based upon the process performed upon the workpiece. A workpiece routing/disposition process is performed based upon modeling an end-of-line (EOL) parameter. The workpiece routing/disposition process includes using a controller to modify the routing plan.
摘要:
A method and an apparatus for selectively processing a layer of a workpiece based upon dependencies with other layers in the workpiece. A process step upon the workpiece is performed. Metrology data relating to the workpiece is acquired. A process adjustment relating to a first layer on the workpiece is calculated based upon the metrology data. A determination whether an error on a second layer on the workpiece would occur in response to an implementation of the process adjustment performed on the first layer. A magnitude of the calculated process adjustment is reduced in response to a determination that the second layer would be affected in response to the implementation of the process adjustment.
摘要:
A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper. The controller is configured to receive a first overlay error measurement associated with the formation of a first layer on a selected wafer and determine at least one parameter in the operating recipe for performing a photolithography process on a second layer formed on the selected wafer based on at least the first overlay error measurement
摘要:
A method and an apparatus for performing feed-forward correction during semiconductor wafer manufacturing. A first process on a semiconductor wafer is performed. Integrated metrology data related to the first process of the semiconductor wafer is acquired. An integrated metrology feed-forward process is performed based upon the integrated metrology data, the integrated metrology feed-forward process comprising identifying at least one error on the semiconductor wafer based upon the integrated metrology data related to the first process of the semiconductor wafer and performing an adjustment process to a second process to be performed on the wafer to compensate for the error. The second process on the semiconductor wafer is performed based upon the adjustment process.
摘要:
A method and an apparatus for performing modeling of batch dynamics in processing of semiconductor wafers. The method includes performing the process on the first semiconductor wafer in a lot, the process being controlled by a tool model, and acquiring integrated metrology data related to the process of the first semiconductor wafer using an integrated metrology tool. The method further includes performing a lot dynamic modeling process based upon an analysis of the integrated metrology data, the lot dynamic modeling process comprising adjusting the tool model based upon analysis of the integrated metrology data, and performing the process on a second semiconductor wafer in the lot based upon the adjusted tool model.
摘要:
A method includes measuring a characteristic of a workpiece at a plurality of locations. A uniformity profile is generated based on the characteristic measurements. At least one acceptable region of the workpiece is identified based on the uniformity profile. At least one unacceptable region of the workpiece is identified based on the uniformity profile. The uniformity profile is filtered to remove at least a portion of the characteristic measurements associated with the second unacceptable region. At least one parameter of an operating recipe for performing a process on the workpiece is determined based on the filtered uniformity profile.
摘要:
A method for controlling a photolithography process includes forming a first layer on a selected wafer. A first overlay error associated with the first layer is measured. At least one parameter in an operating recipe for performing a photolithography process on a second layer formed on the first wafer is determined based on at least the first overlay error measurement. A processing line includes a photolithography stepper, and overlay metrology tool, and a controller. The photolithography stepper is configured to process wafers in accordance with an operating recipe. The overlay metrology tool is configured to measure overlay errors associated with the processing of the wafers in the photolithography stepper. The controller is configured to receive a first overlay error measurement associated with the formation of a first layer on a selected wafer and determine at least one parameter in the operating recipe for performing a photolithography process on a second layer formed on the selected wafer based on at least the first overlay error measurement.
摘要:
A processing line includes a process tool, a metrology tool, a tool state monitor, and a sampling controller. The processing tool is configured to process workpieces. The metrology tool is configured to measure an output characteristic of selected workpieces in accordance with a sampling plan. The tool state monitor is configured to observe at least one tool state variable value during the processing of a selected workpiece in the processing tool. The sampling controller is configured to receive the observed tool state variable value and determine the sampling plan for the metrology tool based on the observed tool state variable value. A method for processing workpieces includes processing a plurality of workpieces in a processing tool. A characteristic of selected workpieces is measured in accordance with a sampling plan. At least one tool state variable value is observed during the processing of a particular workpiece in the processing tool. The sampling plan is determined based on the observed tool state variable value.
摘要:
In one illustrative embodiment, the method comprises providing a plurality of wafer lots, each of the lots comprising a plurality of wafers, performing at least one process operation on at least some of the wafers in each of the plurality of lots, identifying processed wafers having similar characteristics, re-allocating the wafers to lots based upon the identified characteristics, and performing additional processing operations on the identified wafers having similar characteristics in the re-allocated lots. In one illustrative embodiment, the system comprises a first processing tool for performing processing operations on each of a plurality of wafers in each of a plurality of wafer lots, a controller for identifying processed wafers having similar characteristics and re-allocating the wafers to lots based upon the identified characteristics, and a second processing tool adapted to perform additional processing operations on the identified wafers having similar characteristics in the re-allocated lot.