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    Touch display panel and touch sensing unit thereof
    21.
    发明授权
    Touch display panel and touch sensing unit thereof 有权
    触摸显示面板及其触摸感应单元

    公开(公告)号：US08570285B2

    公开(公告)日：2013-10-29

    申请号：US12700737

    申请日：2010-02-05

    Applicant: Hsin-Hung Lee ,  Pei-Yu Chen ,  Yu-Mei Chiu ,  Wei-Jen Chang ,  Yu-Chuan Lin ,  Kuo-Hsing Cheng

    Inventor： Hsin-Hung Lee ,  Pei-Yu Chen ,  Yu-Mei Chiu ,  Wei-Jen Chang ,  Yu-Chuan Lin ,  Kuo-Hsing Cheng

    IPC: G06F3/041

    CPC classification number: G06F3/044 ,  G06F2203/04111

    Abstract: A touch display panel includes a display panel and a touch sensing unit. The touch sensing unit includes first sensing series, and second sensing series. Each of the first sensing series includes a plurality of first transparent sensing pads disposed along a first direction, and a plurality of non-transparent bridge lines disposed along the first direction. Each of the non-transparent bridge lines is disposed between two adjacent first transparent sensing pads, overlapping with two adjacent first transparent sensing pads, and electrically connected to two adjacent first transparent sensing pads. The line width of each non-transparent bridge line is substantially between 0.5 micrometers and 10 micrometers, and the reduction of aperture ratio in a pixel region of the touch display panel caused by the non-transparent bridge lines is substantially between 0.1% and 5%.

    Abstract translation: 触摸显示面板包括显示面板和触摸感测单元。 触摸感测单元包括第一感测系列和第二感测系列。 第一感测系列中的每一个包括沿着第一方向设置的多个第一透明感测垫和沿着第一方向设置的多个不透明的桥线。 每个非透明桥线布置在两个相邻的第一透明感测垫之间，与两个相邻的第一透明感测垫重叠，并且电连接到两个相邻的第一透明感测垫。 每个非透明桥接线的线宽基本上在0.5微米至10微米之间，并且由非透明桥接线引起的触摸显示面板的像素区域中的开口率的减小基本上在0.1％和5％之间， 。

    Shift registers
    23.
    发明授权
    Shift registers 有权
    移位寄存器

    公开(公告)号：US07787585B2

    公开(公告)日：2010-08-31

    申请号：US12402719

    申请日：2009-03-12

    Applicant: Kuo-Hsing Cheng ,  Yao-Jen Hsieh

    Inventor： Kuo-Hsing Cheng ,  Yao-Jen Hsieh

    IPC: G11C19/00

    CPC classification number: G11C19/28 ,  G09G2310/0286

    Abstract: A shift register including shift register units controlled by first and second clock signals for generating an output signal. For each unit, in an active period, the first driving device drives the first switch device to activate the output signal, and the second driving device provides a voltage signal according to the first clock signal to drive the first switch device to de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the voltage signal to serve as the output signal according to the second clock signal. In the active period, the voltage signal has a low level, and the first and second clock signals are set as alternating-current signals and are opposite to each other. In a blanking period, the voltage signal has a high level, and each of the first and second clock signals is set as a direct-current signal.

    Abstract translation: 移位寄存器，包括由第一和第二时钟信号控制的移位寄存器单元，用于产生输出信号。 对于每个单元，在活动期间，第一驱动装置驱动第一开关装置以激活输出信号，并且第二驱动装置根据第一时钟信号提供电压信号，以驱动第一开关装置去激活 输出信号。 当第一开关装置断开输出信号时，第二开关装置根据第二时钟信号提供电压信号作为输出信号。 在有效期间，电压信号为低电平，第一和第二时钟信号被设定为交流信号，彼此相反。 在消隐期间，电压信号具有高电平，并且将第一和第二时钟信号中的每一个设置为直流信号。

    SHIFT REGISTERS
    24.
    发明申请
    SHIFT REGISTERS 有权
    移位寄存器

    公开(公告)号：US20100172461A1

    公开(公告)日：2010-07-08

    申请号：US12407167

    申请日：2009-03-19

    Applicant: Kuo-Hsing Cheng ,  Wai-Pan Wu ,  Kuo-Hsien Lee ,  Chun-Huai Li

    Inventor： Kuo-Hsing Cheng ,  Wai-Pan Wu ,  Kuo-Hsien Lee ,  Chun-Huai Li

    IPC: G11C19/28

    CPC classification number: G11C19/28 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2320/043

    Abstract: A shift register including shift register units substantially cascaded is disclosed. Each shift register unit is controlled by first and second clock signals opposite to each other for generating an output signal. Each shift register unit includes first and second switch devices and first and second devices. The first switch device provides the output signal through an output node. The first driving device drives the first switch device according to a first input signal to activate the output signal. The second driving device provides a first voltage signal, according to the first clock signal, to drive the first switch device and de-activate the output signal. When the first switch device de-activates the output signal, the second switch device provides the second voltage signal to the output node according to the second clock signal. A level of the first voltage signal is lower than a level of the second voltage signal.

    Abstract translation: 公开了一种包括基本级联的移位寄存器单元的移位寄存器。 每个移位寄存器单元由彼此相对的第一和第二时钟信号控制，以产生输出信号。 每个移位寄存器单元包括第一和第二开关器件以及第一和第二器件。 第一开关装置通过输出节点提供输出信号。 第一驱动装置根据第一输入信号驱动第一开关装置以激活输出信号。 第二驱动装置根据第一时钟信号提供第一电压信号以驱动第一开关装置并且去激活输出信号。 当第一开关装置断开输出信号时，第二开关装置根据第二时钟信号向输出节点提供第二电压信号。 第一电压信号的电平低于第二电压信号的电平。

    Clock generators
    25.
    发明申请
    Clock generators 有权
    时钟发生器

    公开(公告)号：US20060290392A1

    公开(公告)日：2006-12-28

    申请号：US11232949

    申请日：2005-09-23

    Applicant: Shu-chang Kuo ,  Wei-Bin Yang ,  Kuo-Hsing Cheng

    Inventor： Shu-chang Kuo ,  Wei-Bin Yang ,  Kuo-Hsing Cheng

    IPC: H03L7/06

    CPC classification number: H03L7/0995 ,  H03K5/133 ,  H03K2005/00065 ,  H03L7/16

    Abstract: Clock generators capable of generating clocks with different frequency according to a binary code. A voltage controlled oscillation module generates a plurality of first clocks (D0˜Dm) with a first frequency (f0), in which the first clocks Di and Di−1 have a fixed phase difference and 1 B and A and B are positive integers.

    Abstract translation: 时钟发生器能够根据二进制码产生不同频率的时钟。 电压控制振荡模块以第一频率（f 0）产生多个第一时钟（D 0→D m），其中第一时钟D < i和D i-1具有固定的相位差和1 1 = A 0 ， A> B和A和B是正整数。

      Display panel and color filter therein
      26.
      发明申请
      Display panel and color filter therein 审中-公开
      显示面板和彩色滤光片

      公开(公告)号：US20060238694A1

      公开(公告)日：2006-10-26

      申请号：US11359511

      申请日：2006-02-23

      Applicant: Wan-Jung Chen ,  Hsueh-Ying Huang ,  Kuo-Hsing Cheng

      Inventor： Wan-Jung Chen ,  Hsueh-Ying Huang ,  Kuo-Hsing Cheng

      IPC: G02F1/1339

      CPC classification number: G02F1/13394 ,  G02F1/133512

      Abstract: A display panel comprising a first substrate, a second substrate and a plurality of pillar spacers is provided. The first substrate comprises a first base and a black matrix layer with a plurality of openings. The black matrix layer is disposed on the lower surface of the first base. The second substrate is disposed below the first substrate and separated at a predetermined distance from the first substrate. The plurality of pillar spacers for maintaining the predetermined distance. Each of the pillar spacer having a first end and a second end. The first end is inserted into the portion of the plurality of openings, and the second end extends to contact with the second substrate.

      Abstract translation: 提供了包括第一基板，第二基板和多个支柱间隔件的显示面板。 第一衬底包括具有多个开口的第一基底和黑色矩阵层。 黑矩阵层设置在第一基座的下表面上。 第二基板设置在第一基板的下方并与第一基板隔开预定的距离。 用于保持预定距离的多个支柱间隔件。 每个柱形隔离物具有第一端和第二端。 第一端插入到多个开口的部分中，第二端延伸以与第二基底接触。

      [DRIVING METHOD OF PIXEL ARRAY]
      27.
      发明申请
      [DRIVING METHOD OF PIXEL ARRAY] 有权
      [像素阵列的驱动方法]

      公开(公告)号：US20050200616A1

      公开(公告)日：2005-09-15

      申请号：US10709715

      申请日：2004-05-24

      Applicant: Kuo-Hsing Cheng

      Inventor： Kuo-Hsing Cheng

      IPC: G09G3/36

      CPC classification number: G09G3/3614 ,  G09G3/3648 ,  G09G2310/0218

      Abstract: A driving method of a pixel array is provided. The driving method is suitable for a pixel array comprising at least one pixel set in each pixel array, wherein at least one pixel set comprises a plurality of pixels. In the driving method, a voltage having substantially same phase is used to drive the pixel electrodes of the pixels in the same pixel set. In addition, voltages with phases substantially opposite to each other are used to drive the pixel electrodes of the pixels in two adjacent pixel sets. Furthermore, a single gate line is used to drive two adjacent pixels in two different pixel sets respectively. In addition, a single gate line is used to drive a first pixel in one of the pixel set and another pixel in an adjacent column of the first pixel, wherein a phase of the voltage of a pixel electrode of the first pixel and a phase of a voltage of a pixel electrode of the other pixel are substantially different.

      Abstract translation: 提供了像素阵列的驱动方法。 驱动方法适用于包括每个像素阵列中的至少一个像素集的像素阵列，其中至少一个像素组包括多个像素。 在驱动方法中，使用具有大致相同相位的电压来驱动同一像素组中的像素的像素电极。 此外，使用相位基本相反的电压来驱动两个相邻像素组中的像素的像素电极。 此外，使用单个栅极线分别驱动两个不同像素集合中的两个相邻像素。 此外，使用单个栅极线来驱动像素组中的一个像素和第一像素的相邻列中的另一像素中的第一像素，其中第一像素的像素电极的电压的相位和 另一像素的像素电极的电压基本上不同。

      Liquid crystal display and liquid crystal display panel thereof
      28.
      发明授权
      Liquid crystal display and liquid crystal display panel thereof 有权
      液晶显示器及其液晶显示面板

      公开(公告)号：US08581888B2

      公开(公告)日：2013-11-12

      申请号：US13097095

      申请日：2011-04-29

      Applicant: Chun-Chi Lai ,  Ching-Wei Chen ,  Tsan-Chun Wang ,  Kuo-Hsing Cheng ,  Yao-Jen Hsieh

      Inventor： Chun-Chi Lai ,  Ching-Wei Chen ,  Tsan-Chun Wang ,  Kuo-Hsing Cheng ,  Yao-Jen Hsieh

      IPC: G09G3/36

      CPC classification number: G09G3/3614 ,  G09G2300/0426

      Abstract: A liquid crystal display (LCD) and an LCD panel thereof are provided. The structure of the pixel array of the LCD panel is the structure of the one third source driving (OTSD), and by which skillfully layout the coupled relationship among each pixel, each signal line and each scan line, such that the LCD panel can be driven by a column inversion to achieve the purpose of single-dot inversion displaying, and thus not only reducing the power consumption of the whole LCD, but also promoting the display quality.

      Abstract translation: 提供液晶显示器（LCD）及其LCD面板。 LCD面板的像素阵列的结构是三分之一源驱动（OTSD）的结构，并且通过其巧妙地布置每个像素，每个信号线和每条扫描线之间的耦合关系，使得LCD面板可以 由列反转驱动，实现单点反转显示的目的，不仅可以降低整个LCD的功耗，还能提高显示质量。

      Clock generator and delta-sigma modulater thereof
      30.
      发明授权
      Clock generator and delta-sigma modulater thereof 有权
      时钟发生器及其Δ-Σ调制器

      公开(公告)号：US08369476B2

      公开(公告)日：2013-02-05

      申请号：US13041437

      申请日：2011-03-07

      Applicant: Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

      Inventor： Wei-Sheng Tseng ,  Hong-Yi Huang ,  Kuo-Hsing Cheng ,  Yuan-Hua Chu

      IPC: H03K21/00 ,  H03K23/00

      CPC classification number: H03L7/1976 ,  G06F1/08 ,  H03K23/68

      Abstract: A clock generator is illustrated. The clock generator mentioned above includes a multimodulus frequency divider and a delta-sigma modulator. The multimodulus frequency divider is archived by switching the phase thereof. The multimodulus frequency divider increases the operating frequency of the clock generator effectively, and has a characteristic with half period resolution for reducing the jitter of an output clock signal when its spectrum is spread. Besides, the delta-sigma modulator increases the accuracy of the triangle modulation and reduces error of quantization by adding a few components therein. Thus, the clock generator could be expanded to a programmable clock generator.

      Abstract translation: 示出了时钟发生器。 上述时钟发生器包括多模式分频器和Δ-Σ调制器。 多模式分频器通过切换其相位进行归档。 多模分频器有效地增加了时钟发生器的工作频率，并且具有半周期分辨率的特性，用于在其频谱扩展时减少输出时钟信号的抖动。 此外，Δ-Σ调制器通过在其中添加几个分量来增加三角形调制的精度并减少量化误差。 因此，时钟发生器可以扩展到可编程时钟发生器。

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