Die-attach method to compensate for thermal expansion

    公开(公告)号:US11430744B2

    公开(公告)日:2022-08-30

    申请号:US15673734

    申请日:2017-08-10

    Applicant: Cree, Inc.

    Abstract: In sonic examples, a method includes pre-stressing a flange, heating the flange to a die-attach temperature, and attaching a die to the flange at the die-attach temperature using a die-attach material. In some examples, the flange includes a metal material, the die-attach temperature may be at least two hundred degrees Celsius, and the die-attach material may include solder and/or an adhesive. In some examples, the method includes cooling the semiconductor die and metal flange to a room temperature after attaching the semiconductor die to the metal flange at the die-attach temperature using a die-attach material.

    PACKAGED RF POWER DEVICE WITH PCB ROUTING

    公开(公告)号:US20220157671A1

    公开(公告)日:2022-05-19

    申请号:US17097294

    申请日:2020-11-13

    Applicant: Cree, Inc.

    Abstract: A radio frequency (RF) transistor amplifier includes a package submount. a package frame comprising an electrically insulating member and one or more conductive layers on the package submount and exposing a surface thereof, a transistor die on the surface of the package submount and comprising respective terminals that are electrically connected to the package frame, a protective member covering the transistor die, and one or more electrical components that are attached to the package frame outside the protective member. Related RF power device packages and fabrication methods are also discussed.

    Methods for dicing semiconductor wafers and semiconductor devices made by the methods

    公开(公告)号:US11289378B2

    公开(公告)日:2022-03-29

    申请号:US16440063

    申请日:2019-06-13

    Applicant: Cree, Inc.

    Abstract: A method for forming semiconductor devices from a semiconductor wafer includes cutting a first surface of a semiconductor wafer to form a first region that extends partially through the semiconductor wafer and the first region has a bottom portion. The method further includes directing a beam of laser light to the semiconductor wafer such that the beam of laser light is focused within the semiconductor wafer between the first surface and the second surface thereof and the beam of laser light further cuts the semiconductor wafer by material ablation to form a second region aligned with the first region. A resulting semiconductor device is disclosed as well.

    RADIO FREQUENCY AMPLIFIERS HAVING IMPROVED SHUNT MATCHING CIRCUITS

    公开(公告)号:US20210210444A1

    公开(公告)日:2021-07-08

    申请号:US16737188

    申请日:2020-01-08

    Applicant: Cree, Inc.

    Abstract: RF amplifiers are provided that include a submount such as a thermally conductive flange. A dielectric substrate is mounted on an upper surface of the submount, the dielectric substrate having a first outer sidewall, a second outer sidewall that is opposite and substantially parallel to the first outer sidewall, and an interior opening. An RF amplifier die is mounted on the submount within the interior opening of the dielectric substrate, where a longitudinal axis of the RF amplifier die defines a first axis. The RF amplifier die is positioned so that a first angle defined by the intersection of the first axis with the first outer sidewall is between 5° and 45°. The dielectric substrate may be a ceramic substrate or a dielectric layer of a printed circuit board.

    Multi-Cavity Package Having Single Metal Flange

    公开(公告)号:US20200035660A1

    公开(公告)日:2020-01-30

    申请号:US16589624

    申请日:2019-10-01

    Applicant: Cree, Inc.

    Abstract: A multi-cavity package includes a single metal flange having first and second opposing main surfaces. The multi-cavity package also includes a circuit board attached to the first main surface of the single metal flange. The circuit board includes a first surface facing the single metal flange, and a second surface facing away from the first surface. The circuit board also includes a plurality of openings exposing different regions of the first main surface of the single metal flange. The circuit board also includes a lateral extension that overhangs the single metal flange. A corresponding method of manufacturing is also provided.

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